(完整版)现代逻辑设计英文试卷A-2014

中国计量学院2013~2014学年第2学期《现代逻辑设计》课程试卷（A）第1页共5页中国计量学院2013~2014学年第2学期《现代逻辑设计》课程考试试卷（A）开课二级学院：信息工程学院，考试时间：2014年6月日时考试形式：闭卷□、开卷□，允许带入场装订线考生姓名：学号：专业：装订线题序一二三四五六七八九总分得分评卷人Fillintheblanks.(total20/100,2foreachblank)1、Y=(sel)?(A+B):(A-B);ifthevalueofselis1，theresultofYisA+B,otherwisetheresultofYisA-B.Theoperator“?:”iscalled_条件运算符____.2、TheexpandnameofgraphicfileinQuartusIIispdfandtheexpandnameofwaveformfileisvwf.3、Thebinaryformof8’h3fis____8’b00111111_______________.4、Thegeneralsymbolofblockingstatementis=.Thegeneralsymbolofnon-blockingstatementis<=.5、AssumedA=2’b11,B=4’b1001,thevalueof“{A,B}”is___6’b111001_,thevalueof“^b”is___0_____.二、Short-answerquestions.(total20/100)1、InVerilogHDL，what’sthemeaningof“always@(posedgeclk)”and“always@(clk)”?(6/100)第一个表示在时钟上升沿触发，第二个表示在时钟高电平触发。一个是边沿敏感，一个是电平敏感。2、FiniteStateMachine(FSM)canbedividedintotwotypesaccordingtothegenerationofoutputvalues.What’sthedifferencebetweenthesetwomodels?(6/100)根据输出信号产生方法的不同，状态机可分为两类：mealy和moore。Moore型状态机的输出仅取决于当前状态，mealy型状态机的输出取决于当前状态和当前输入。3．PleaseexplainthestructureofaVerilogmodulewithexamples.(8/100)四个部分：模块申明、端口定义、数据类型定义、功能描述。Givethedefinitionofthevariablesandconstants.(total12/100,3foreach)Definean8-bitbusofwiretypenamed“ABUS”.wire[7:0]ABUS;Definea16-bitvariableofregtypenamed“address”.reg[15:0]address;装订线Defineaparameternamed“delay_time”装订线parameterdelay_time=8;Defineamemorywiththewordwidthof32andmemorysizeof128.reg[31:0]memory[127:0];四、Programcomprehension.(total16/100)1、Pleasecorrecttheprogramofan4-bitcomparatorwhichhastwo4-bitinputsaandbandthreeoutputsa_gt_b,a_eq_banda_lt_b.（8/100）module4bit_comp(a,b,a_gt_b,a_eq_b,a_lt_b);input[7:0]a,b;outputa_gt_b,a_eq_b,a_lt_b;rega_gt_b,a_eq_b,a_lt_b;assign a_gt_b=(a>b), a_eq_b=(a=b), a_lt_b=(a<b);endmoduleThisprogramisa3-8decoderwhichhasanenablesignal“en”.When“en”islogic1,thedecoderworksindecodingmode.Fillintheblanks.(8/100)moduledecoder(a,y,en);input[2:0]a;inputen;output[7:0]y__________________;reg[7:0]y__________________;always@(aoren)if(en=1)begincase(a)____________;3’b000:y=8’b11111110;3’b001:y=8’b11111101;3’b010:y=8’b11111011;3’b011:y=8’b11110111;___________11101111;____________;3’b101:y=8’b11011111;3’b110:y=8’b10111111;3’b111:y=8’b01111111;default:y=8’b11111111;endelsey=8’b11111111;endmodule五、Programming(total32/100）1、Accordingtotheschematicdiagram,pleasedesigna2-1MUXinstructuralstyle(usingbuilt-inprimitives).(8/100)modulemux(OUT,A,B,SEL);outputOUT;inputA,B,SEL;notI5(sel_n,SEL);andI6(sel_a,A,SEL);andI7(sel_b,sel_n,B);orI4(OUT,sel_a,sel_b);