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ComputerSystemsOrganizationandArchitecture-SolutionsManual
PAGE
3
Copyright2001AddisonWesley-AllRightsReserved Page
PAGE
ii
SOLUTIONSMANUAL
ComputerSystemsOrganization
andArchitecture
JohnD.Carpinelli
Copyright©2001,AddisonWesleyLongman-AllRightsReserved
TableofContents
TOC\o"1-3"
Chapter1
1
Chapter2
8
Chapter3
18
Chapter4
21
Chapter5
33
Chapter6
45
Chapter7
59
Chapter8
80
Chapter9
92
Chapter10
100
Chapter11
106
Chapter12
116
ComputerSystemsOrganizationandArchitecture-SolutionsManual
Copyright2001AddisonWesley-AllRightsReserved Page
PAGE
30
Chapter1
1.
x
y
z
x+y´
y+z
(x+y´)(y+z)
xy
xz
y´z
xy+xz+y´z
0
0
0
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
0
1
2.a)
w
x
y
z
wx
xz
y´
wx+xz+y´
b)
w
x
y
z
w+x+y+z
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
0
1
0
1
0
0
1
1
0
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
1
1
0
1
0
1
1
0
1
1
0
0
0
0
0
0
1
1
0
1
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
0
0
0
0
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
1
0
0
1
1
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0
0
1
0
1
1
1
1
1
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
0
1
0
0
1
1
1
1
0
1
1
1
1
1
1
1
0
1
1
1
1
1
1
c)
w
x
y
z
w´x´yz
w´xyz
w´x´yz´
w´xyz´
w´x´yz+w´xyz+w´x´yz´+w´xyz´
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
1
1
1
0
0
0
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
1
1
1
0
1
0
0
1
1
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
3.
a
b
ab
(ab)´
a´
b´
a´+b´
a
b
a+b
(a+b)´
a´
b´
a´b´
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
0
1
0
1
1
0
1
0
0
1
0
0
1
0
1
1
1
0
1
0
0
1
0
1
1
1
0
0
0
0
1
1
1
0
0
0
0
4.a) w'+x'+y'+z'
w'+x'+y'z
(w'+x')+(w'+y')+(w'+z')+(x'+y')+(x'+z')+(y'+z')=w'+x'+y'+z'
5.a)
wx\yz
00
01
11
10
b)
wx\yz
00
01
11
10
00
1
1
0
0
00
1
1
0
1
01
0
1
1
0
01
1
1
1
0
11
0
0
1
1
11
1
1
1
0
10
1
0
0
1
10
1
0
0
1
w´x´y´+w´xz+wxy+wx´z´ x´z´+w´y´+xz+xy´
or or
x´y´z´+w´y´z+xyz+wyz´ x´z´+w´y´+xz+y´z´
6.a)
wx\yz
00
01
11
10
b)
wx\yz
00
01
11
10
00
1
0
0
1
00
X
1
1
X
01
1
X
1
1
01
0
X
X
0
11
0
1
X
0
11
0
0
X
0
10
0
X
X
0
10
X
X
X
X
w´z´+xy x´
7.a)
wx\yz
00
01
11
10
b)
wx\yz
00
01
11
10
c)
wx\yz
00
01
11
10
00
0
1
0
0
00
1
0
0
0
00
0
1
0
1
01
0
1
1
0
01
1
1
0
0
01
1
0
1
0
11
1
1
1
1
11
1
1
0
1
11
0
1
0
1
10
0
0
0
0
10
1
0
0
1
10
1
0
1
0
wx+xz+w´y´z y´z´+xy´+wz´ Alreadyminimal
a)b)c)
9.wxy´+wxz+w´xy+xyz´:
wx\yz
00
01
11
10
00
0
0
0
0
01
0
0
1
1
11
1
1
1
1
10
0
0
0
0
wx+xy
10.a) b)
11. ChangetheANDgatestoNANDgates.Therestofthecircuitisunchanged.
12. Removethetri-statebuffersanddooneofthefollowing:
Changeeach2-inputANDgatetoa3-inputANDgate.Eachgates'inputsshouldbeitstwooriginalinputsandE,or
HaveeachANDgate'soutputserveasaninputtoanother2-inputANDgate,onegateforeachoriginalANDgate.Thesecondinputtothenew2-inputANDgatesisE.
13.
14.
SetupKarnaughmapsforeachoutput,thendevelopminimallogicexpressionsanddesigntheappropriatelogiccircuits.
X>Y:
X1X0\Y1Y0
00
01
11
10
X=Y:
X1X0\Y1Y0
00
01
11
10
X<Y:
X1X0\Y1Y0
00
01
11
10
00
0
0
0
0
00
1
0
0
0
00
0
1
1
1
01
1
0
0
0
01
0
1
0
0
01
0
0
1
1
11
1
1
0
1
11
0
0
1
0
11
0
0
0
0
10
1
1
0
0
10
0
0
0
1
10
0
0
1
0
(X>Y)=X1Y1'+X0Y1'Y0'+X1X0Y0'
(X=Y)=X1'X0'Y1'Y0'+X1'X0Y1'Y0+X1X0'Y1Y0'+X1X0Y1Y0=(X1Y1)'(X0Y0)'
(X<Y)=X1'Y1+X1'X0'Y0+X0'Y1Y0
16. C3=X2Y2+(X2Y2)(X1Y1+(X1Y1)(X0Y0+(X0Y0)C0))
C4=X3Y3+(X3Y3)(X2Y2+(X2Y2)(X1Y1+(X1Y1)(X0Y0+(X0Y0)C0)))
17.
18
X3X2\X1X0
00
01
11
10
X3X2\X1X0
00
01
11
10
00
1
0
1
1
00
1
0
0
1
01
0
1
0
1
01
0
0
0
1
11
X
X
X
X
11
X
X
X
X
10
1
0
X
X
10
1
0
X
X
d=X2'X0'+X2'X1+X1X0'+X2X1'X0 e=X2'X0'+X1X0'
X3X2\X1X0
00
01
11
10
X3X2\X1X0
00
01
11
10
00
1
0
0
0
00
0
0
1
1
01
1
1
0
1
01
1
1
0
1
11
X
X
X
X
11
X
X
X
X
10
1
1
X
X
10
1
1
X
X
f=X3+X2X0'+X2X1'+X1'X0' g=X3+X2X0'+X1X0'+X2'X1
19.
X3
X2
X1
X0
a
b
c
d
e
f
g
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
0
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
1
0
0
0
0
1
1
0
0
1
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
a:
X3X2\X1X0
00
01
11
10
b:
X3X2\X1X0
00
01
11
10
c:
X3X2\X1X0
00
01
11
10
00
0
1
0
0
00
0
0
0
0
00
0
0
0
1
01
1
0
0
0
01
0
1
0
1
01
0
0
0
0
11
X
X
X
X
11
X
X
X
X
11
X
X
X
X
10
0
0
X
X
10
0
0
X
X
10
0
0
X
X
a=X3'X2'X1'X0+X2X1'X0' b=X2X1'X0+X2X1X0' c=X2'X1X0'
d:
X3X2\X1X0
00
01
11
10
e:
X3X2\X1X0
00
01
11
10
f:
X3X2\X1X0
00
01
11
10
00
0
1
0
0
00
0
1
1
0
00
0
1
1
1
01
1
0
1
0
01
1
1
1
0
01
0
0
1
0
11
X
X
X
X
11
X
X
X
X
11
X
X
X
X
10
0
1
X
X
10
0
1
X
X
10
0
0
X
X
d=X2X1'X0'+X2'X1'X0+X2X1X0 e=X2X1'+X0 f=X1X0+X3'X2'X0+X2'X1
g:
X3X2\X1X0
00
01
11
10
00
1
1
0
0
01
0
0
1
0
11
X
X
X
X
10
0
0
X
X
g=X3'X2'X1'+X2X1X0
Thefourinputscanbeinoneof24(=4!)possibleorders.Sinceeachsorterhastwopossiblestates(MAX=XMIN=Y,orMAX=YMIN=X),nsorterscanhaveupto2nstates.Foursorterscanhaveonly24=16states,notenoughtosortall24possibleinputorders.Fivesortershave25=32states,whichcouldbesufficient.(Thisargumentestablishesalowerbound;itdoesnotguaranteetheexistenceofa5-sorternetworkthatcansortfourinputs.SincethesortingnetworkofFigure1.24(b)matchesthisbound,itisaminimalnetwork.)
21.a) b)
22. Aflip-flopisclockediftheincrementsignalandclockareasserted,andallflip-flopstoitsrightare1.
EachclockisdrivenbyQoftheflip-floptoitsrightinsteadofQ'.Theclockoftherightmostflip-flopisunchanged.Allothersignalsareunchanged.
24.
X2
X1
X0
Q2
Q1
Q0
J2
K2
J1
K1
J0
K0
0
0
0
0
0
1
0
X
0
X
1
X
0
0
1
0
1
1
0
X
1
X
X
0
0
1
0
1
1
0
1
X
X
0
0
X
0
1
1
0
1
0
0
X
X
0
X
1
1
0
0
0
0
0
X
1
0
X
0
X
1
0
1
1
0
0
X
0
0
X
X
1
1
1
0
1
1
1
X
0
X
0
1
X
1
1
1
1
0
1
X
0
X
1
X
0
J2:
X2\X1X0
00
01
11
10
J1:
X2\X1X0
00
01
11
10
J0:
X2\X1X0
00
01
11
10
0
0
0
0
1
0
0
1
X
X
0
1
X
X
0
1
X
X
X
X
1
0
0
X
X
1
0
X
X
1
J2=X1X0' J1=X2'X0 J0=X2'X1'+X2X1
K2:
X2\X1X0
00
01
11
10
K1:
X2\X1X0
00
01
11
10
K0:
X2\X1X0
00
01
11
10
0
X
X
X
X
0
X
X
0
0
0
X
0
1
X
1
1
0
0
0
1
X
X
1
0
1
X
1
0
X
K2=X1'X0' K1=X2X0 K0=X2'X1+X2X1'
25.a) b)
26.a) b)
27.
Chapter2
1.a)
PresentState
D
NextState
0
0
0
0
1
1
1
0
0
1
1
1
b)
PresentState
T
NextState
0
0
0
0
1
1
1
0
1
1
1
0
2.
PresentState
S
R
NextState
0
0
0
0
0
0
1
0
0
1
0
1
0
1
1
U
1
0
0
1
1
0
1
0
1
1
0
1
1
1
1
U
U
0
0
U
U
0
1
0
U
1
0
1
U
1
1
U
3. Addthefollowingstatestothestatetable.Sincealladditionsareself-loops,itisnotnecessarytochangethestatediagram.
PresentState
C
I1
I0
NextState
R
G
A
SNOCAR
0
0
1
SNOCAR
1
0
0
SNOCAR
0
1
0
SNOCAR
1
0
0
SNOCAR
0
1
1
SNOCAR
1
0
0
SPAID
1
0
1
SPAID
0
1
0
SPAID
1
1
0
SPAID
0
1
0
SPAID
1
1
1
SPAID
0
1
0
SCHEAT
0
0
1
SCHEAT
1
0
1
SCHEAT
0
1
0
SCHEAT
1
0
1
SCHEAT
0
1
1
SCHEAT
1
0
1
4.
5.
6.
Address
Data(Mealy)
Data(Moore)
0000
0000
0000
0001
0010
0010
0010
0100
0100
0011
0110
0110
0100
1000
1000
0101
1010
1010
0110
1101
1100
0111
1110
1110
1000
0000
0000
1001
0010
0010
1010
0100
0100
1011
0110
0110
1100
1000
1001
1101
1010
1011
1110
1101
1100
1111
1110
1110
7.
PresentState
I
NextState
M
00
0
00
0
00
1
01
0
01
0
00
0
01
1
10
0
10
0
11
0
10
1
10
0
11
0
00
1
11
1
01
1
N1=P1'P0I+P1P0'
N0=P1'P0'I+P1P0'I'+P1P0I
M=P1P0
8.
9.
Address
Data(Mealy)
Data(Moore)
000
000
000
001
010
010
010
000
000
011
100
100
100
111
110
101
100
100
110
000
001
111
010
011
10. Statevalueassignments(P3-P0): S0=0000 S5=0001 S10=0010 S15=0011 S20=0100 S25=0101 S30=0110 SPAID=0111 SNOCAR=1000 SCHEAT=1001
N3=C'
N2=P3'CI1I0+P3'(P2+P1)CI1I0'+P3'(P2+P1P0)CI1'I0+P2CI1'I0'
N1=P3'(P2+P1+P0)CI1I0+P3'(P2+P1')CI1I0'+P3'(P1'P0+P1P0'+P2P1P0)CI1'I0+P1P0CI1'I0'
N0=P3'(P2+P1+P0')CI1I0+P3'(P0+P2P1)CI1I0'+P3'(P0'+P2P1)CI1'I0+P3'P0CI1'I0'+P3P0C +P3'(P2'+P1'+P0')C'
R=SPAID'
G=SPAID
A=SCHEAT
11. Statevalueassignments(P3-P0): S0=0000 S5=0001 S10=0010 S15=0011 S20=0100 S25=0101 S30=0110 SPAID=0111 SNOCAR=1000 SCHEAT=1001
N3=C'
N2=P3'CI1I0+P3'(P2+P1)CI1I0'+P3'(P2+P1P0)CI1'I0+P2CI1'I0'
N1=P3'(P2+P1+P0)CI1I0+P3'(P2+P1')CI1I0'+P3'(P1'P0+P1P0'+P2P1P0)CI1'I0+P1P0CI1'I0'
N0=P3'(P2+P1+P0')CI1I0+P3'(P0+P2P1)CI1I0'+P3'(P0'+P2P1)CI1'I0+P3'P0CI1'I0'+P3P0C +P3'(P2'+P1'+P0')C'
R=G'
G=P3'(P2+P1)CI1I0+P3'P2P0CI1+P3'P2P1C(I1+I0)+P3'P2P1P0C
A=P3'(P2+P1+P0)C'
12.
Address
Data
0000XXX
10011011001101100110110011010000100000110000101000101100
0001XXX
10011011001101100110110011010001100001010000111000110100
0010XXX
10011011001101100110110011010010100001110001001000111010
0011XXX
10011011001101100110110011010011100010010001011000111010
0100XXX
10011011001101100110110011010100100010110001101000111010
0101XXX
10011011001101100110110011010101100011010001110100111010
0110XXX
10011011001101100110110011010110100011101001110100111010
0111XXX
10001001000100100010010001000111010011101001110100111010
1000XXX
10001001000100100010010001000000100000010000001000000100
1001XXX
10011011001101100110110011010000100000010000001000000100
1010XXX
10001001000100100010010001001000100100010010001001000100
1011XXX
10001001000100100010010001001000100100010010001001000100
1100XXX
10001001000100100010010001001000100100010010001001000100
1101XXX
10001001000100100010010001001000100100010010001001000100
1110XXX
10001001000100100010010001001000100100010010001001000100
1111XXX
10001001000100100010010001001000100100010010001001000100
13. N2:
P2P1\P0U
00
01
11
10
N1:
P2P1\P0U
00
01
11
10
N2:
P2P1\P0U
00
01
11
10
00
0
0
0
0
00
0
0
1
0
00
0
1
0
1
01
0
0
1
0
01
1
1
0
1
01
0
1
0
1
11
0
0
0
0
11
0
0
0
0
11
0
0
0
0
10
1
1
0
1
10
0
0
0
0
10
0
1
0
1
ThenextstatelogicisthesameasfortheMooremachine.
N2=P2P0'+P2U'+P1P0U
N1=P1P0'+P1U'+P2'P1'P0U
N0=P0'U+P0U'
C=P2'P1'P0'U'+P2P1'P0U
V2=P2'P1P0U+P2P1'P0'+P2P1'P0U'
V1=P2'P1'P0U+P2'P1P0'+P2'P1P0U'
V0=(P2'+P1')P0'U+(P2'+P1)P0U'
15. Allpossiblenextstatevaluesarealreadyused.
16. Statevalueassignments(P3-P0): S0=0000 S5=0001 S10=0010 S15=0011 S20=0100 S25=0101 S30=0110 SPAID=0111 SNOCAR=1000 SCHEAT=1001 SA=1010
SB=1011 SC=1100 SD=1101 SE=1110 SF=1111
Addtostatetable:
PresentState
C
I1
I0
NextState
R
G
A
1010
X
X
X
1000
0
0
0
1011
X
X
X
1000
0
0
0
1100
X
X
X
1000
0
0
0
1101
X
X
X
1000
0
0
0
1110
X
X
X
1000
0
0
0
1111
X
X
X
1000
0
0
0
Addtostatediagram:
N3=C'+P3(P2+P1)
N2=P3'CI1I0+P3'(P2+P1)CI1I0'+P3'(P2+P1P0)CI1'I0+P2CI1'I0'
N1=P3'(P2+P1+P0)CI1I0+P3'(P2+P1')CI1I0'+P3'(P1'P0+P1P0'+P2P1P0)CI1'I0+P1P0CI1'I0'
N0=P3'(P2+P1+P0')CI1I0+P3'(P0+P2P1)CI1I0'+P3'(P0'+P2P1)CI1'I0+P3'P0CI1'I0'+P3P0C +P3'(P2'+P1'+P0')C'
R=SPAID'
G=SPAID
A=SCHEAT
17. N3=P2P1P0U'+P3(P2'+P1'+P0'+U)
N2=P3P2(P0+U)+P2P1+P3'P1P0'U'
N1=P3'(P2+P1)U'+P2P1P0U'+P1U
N0=(P3'+P2)P1'U+P3'P2U+P0U'
C=P2'P1'P0'
V2=P3P1'P0+P3P2P0'
V1=P3'P1P0'+P2P1P0
V0=P3'P2'P0+P2P1P0+P3P1'P0
18.
19.
20. StatesareoftheformABCYZ,whereA|B|C=0ifaplayermaysignal,or1iftheplayermaynotsignal.YZrepresentstheplayeransweringthequestion(01=player1,10=player2,11=player3,00=noplayer).Althoughnotshowninthediagram,thereisanarcfromeverystatebacktostate00000withconditionR.
Address
Data
Address
Data
Address
Data
XXXXXXX1X
00000000
00110XX00
00110010
10010XX00
10010010
00000000X
00000000
00110XX01
01100010
10010XX01
11000010
00000010X
00001000
01000X00X
01000000
10011XX00
10011001
00000100X
00010000
01000010X
01001000
10011XX01
10100001
00000110X
00011000
01000110X
01011000
101000X0X
10100000
00001XX00
00001100
01001XX00
01001100
10100100X
10110000
00001XX01
10000100
01001XX01
11000100
10100110X
10100000
00010XX00
00010010
01011XX00
01011001
10110XX00
10110010
00010XX01
01000010
01011XX01
01100001
10110XX01
11100010
00011XX00
00011001
01100000X
01100000
110000X0X
11000000
00011XX01
00100001
01100010X
01101000
11000100X
11000000
00100000X
00100000
011001X0X
01100000
11000110X
11011000
00100010X
00101000
01101XX00
01101100
11011XX00
11011001
00100100X
00110000
01101XX01
11100100
11011XX01
11100001
00100110X
00100000
100000X0X
10000000
11100XX0X
11100000
00101XX00
00101100
10000100X
10010000
Allothers
00000000
00101XX01
10100100
10000110X
10011000
21. StatesareoftheformABCYZ,whereA|B|C=0ifaplayermaysignal,or1iftheplayermaynotsignal.YZrepresentstheplayeransweringthequestion(01=player1,10=player2,11=player3,00=noplayer).Althoughnotshowninthediagram,thereisanarcfromeverystatebacktostate00000withconditionR.
Address
Data
Address
Data
Address
Data
XXXXXXX1X
00000000
00110XX00
00110010
10010XX00
10010010
00000000X
00000000
00110XX01
01100000
10010XX01
11000000
00000010X
00001100
01000X00X
01000000
10011XX00
10011001
00000100X
00010010
01000010X
01001100
10011XX01
10100000
00000110X
00011001
01000110X
01011001
101000X0X
10100000
00001XX00
00001100
01001XX00
01001100
10100100X
10110010
00001XX01
10000000
01001XX01
11000000
10100110X
10100000
00010XX00
00010010
01011XX00
01011001
10110XX00
10110010
00010XX01
01000000
01011XX01
01100000
10110XX01
11100000
00011XX00
00011001
01100000X
01100000
110000X0X
11000000
00011XX01
00100000
01100010X
01101100
11000100X
11000000
00100000X
00100000
011001X0X
01100000
11000110X
11011001
00100010X
00101100
01101XX00
01101100
11011XX00
11011001
00100100X
00110010
01101XX01
11100000
11011XX01
11100000
00100110X
00100000
100000X0X
10000000
11100XX0X
11100000
00101XX00
00101100
10000100X
10010010
Allothers
00000000
00101XX01
10100000
10000110X
10011001
22.
23.
24.
25. P1: P0X'YshouldbeP0XY
P0: P0XY'shouldbeP0X'Y'
B: P0shouldbeP0'
26. CLR: 0XY'shouldbe1XY'
CounterinputD0: 0X'Yshouldbe0XY
A: 1shouldbe0
27.
Address
CorrectData
0011
01110
0100
01011
1011
00111
Chapter3
1. a)Datamovement b)Dataoperation c)Programcontrol d)Dataoperation e)Dataoperation
2. a)Dataoperation b)Programcontrol c)Datamovement d)Datamovement e)Dataoperation
3. a)Direct b)Implied c)Implicit
4. a)Implicit b)Direct c)Implicit
5. a)Implicit b)Direct c)Implicit
6. a)RegisterDirect b)Immediate c)Implicit d)Immediate e)Direct
7. a)Implicit b)Direct c)Indirect d)RegisterIndirect e)RegisterDirect
8. a)RegisterDirect b)RegisterIndirect c)Implicit d)Implicit e)Immediate
9. a)AC=11 b)AC=12 c)AC=10 d)AC=11 e)AC=10 f)AC=33 g)AC=41
10. a)AC=11 b)AC=12 c)AC=30 d)AC=31 e)AC=10 f)AC=23 g)AC=31
11. a)AC=11 b)AC=12 c)AC=20 d)AC=21 e)AC=10 f)AC=43 g)AC=21
12.a)
MULX,B,C
b)
MOVX,B
c)
LOADB
d)
PUSHA
ADDX,X,A
MULX,C
MULC
PUSHB
ADDX,X,D
ADDX,A
ADDA
PUSHC
ADDX,D
ADDD
MUL
STOREX
PUSHD
ADD
ADD
POPX
13.a)
MULT,A,B
b)
MOVT,A
c)
LOADA
d)
PUSHA
MULT,T,C
MULT,B
MULB
PUSHB
ADDX,E,F
MULT,C
MULC
MUL
MULX,X,D
MOVX,E
STORET
PUSHC
ADDX,X,T
ADDX,F
LOADE
MUL
MULX,D
ADDF
PUSHD
ADDX,T
MULTD
PUSHE
ADDT
PUSHF
STOREX
ADD
MUL
ADD
POPX
14.a)
MULX,B,C
b)
MOVT,B
c)
LOADB
d)
PUSHA
SUBX,A,X
MULT,C
MULC
PUSHB
MULT,E,F
MOVX,A
STORET
PUSHC
ADDT,T,D
SUBX,T
LOADA
MUL
MULX,X,T
MOVT,E
SUBT
SUB
MULT,F
STOREX
PUSHD
ADDT,D
LOADE
PUSHE
MULX,T
MULF
PUSHF
ADDD
MUL
MULX
ADD
STOREX
MUL
POPX
15.
Processor
Timeperinstruction
#Instructions
Totaltime
0
35ns
4
140ns
1
50ns
3
150ns
2
70ns
2
140ns
3
100ns
1
100ns
←fastest
16.
Processor
Timeperinstruction
#Instructions
Totaltime
0
35ns
8
280ns
1
50ns
5
250ns
←fastest
2
70ns
4
280ns
3
100ns
3
300ns
17.
Processor
Timeperinstruction
#Instructions
Totaltime
0
35ns
12
420ns
←fastest
1
50ns
9
450ns
2
70ns
7
490ns
3
100ns
5
500ns
18.
Processor
Timeperinstruction
#Instructions
Totaltime
0
35ns
12
420ns
←fastest
1
50ns
11
550ns
2
70ns
8
560ns
3
100ns
5
500ns
19.
LDAC1001H
MVAC
LDAC1002H
ADD
MVAC
LDAC1003H
ADD
MVAC
LDAC1004H
ADD
MVAC
LDAC1005H
ADD
MVAC
LDAC1006H
ADD
MVAC
LDAC1007H
ADD
MVAC
LDAC1008H
ADD
MVAC
LDAC1009H
ADD
MVAC
LDAC100AH
ADD
STAC1000H
20.
Loop:
LXIH,1001H
MVIB,0AH
XRAA
ADDM
INXH
DCRB
JNZLoop
STA1000H
21.
Loop:
CLAC
INAC
STACFA
INAC
STACFB
STACCount
STACFN
MVAC
LDAC
SUB
JMPZDone
LDACFA
MVAC
LDACFB
ADD
STACFA
LDACCount
INAC
STACCount
MVAC
LDACn
SUB
JMPZDoneA
FA=1
FB=2
Count=2
FN=2
Ifn=2thendone
FA=FA+FB
Count=Count+1
IfCount=nthen
done,resultinFA
DoneA:
DoneB:
Done:
LDACFB
MVAC
LDACFA
ADD
STACFB
LDACCount
INAC
STACCount
MVAC
LDACn
SUB
JMPZDoneB
JUMPLoop
LDACFA
STACFN
JUMPDone
LDACFB
STACFN
…
FB=FB+FA
Count=Count+1
IfCount=nthen
done,resultinFB
Notdone,loopback
FN=FA
FN=FB
22.
Loop:
Done:
LDAn
MOVD,A
MVIB,1
MVIA,2
MOVC,A
DCRD
DCRD
JZDone
ADDB
MOVB,A
DCRD
JZDone
ADDC
MOVC,A
DCRD
JNZLoop
STAFN
D=n
B=FA
C=FB
InitiallyA=FA
FA=FA+FB
IfD=0thendone
FB=FB+FA
IfD=0thendone
Notdone,loopback
StoreFN
Chapter4
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. a.) CE=A7'A6'A5'A4'()' OE=RD
CE=A7'A6'A5'A4()' OE=RD
c.) CE=A7A6A5A4()' OE=RD
11.
BigEndian
LittleEndian
a)
12H
23 34H
24 56H
25 78H
78H
23 56H
24 34H
25 12H
b)
09H
23 27H
27H
23 09H
c)
05H
23 55H
24 12H
25 12H
12H
23 12H
24 55H
25 05H
12. Starteachvalueatlocation4X,whereXI0,20forexample.
13.
14. Thisisthesameasthepreviousproblem,exceptisnotincluded.
15.
16. Thisisthesameasthepreviousproblem,exceptisnotincluded.
17.
18. Thisisthesameasthepreviousproblem,exceptisnotincluded.
19.
20.
21.
22. Memorysubsystem:
22(continued). I/Osubsystem:
Chapter5
1. a) :WX,YZ
b) :WX
':YZ
c) ':WX
a)b)c)
3. a) :XY
:XY'
b) :X0
:XX'
a)b)
5.
6. a)b)
c)
7.
8. a) 0011001000000100
b) 0100110010000001
c) 0011001000000101
d) 0100110010000001
e) 1011001000000100
f) 1100110010000001
g) 1001000000100000
h) 0000100110010000
9. a) 0000011100101010
b) 0100000111001010
c) 0000011100101011
d) 1100000111001010
e) 1000011100101010
f) 1100000111001010
g) 0011100101010000
h) 0000100000111001
10. a) 1011001011110000
b) 0010110010111100
c) 1011001011110000
d) 0010110010111100
e) 0011001011110000
f) 0010110010111100
g) 1001011110000000
h) 0000010110010111
a)
b)
c)
d)
a)
b)
c)d)
13. a) X0,X[(n-2)-1]
b) XX[(n-2)-0,(n-1)]
c) XX[0,(n-1)-1]
d) X[(n-2)-0]X[(n-3)-0],0
e) X[(n-2)-0]X[(n-1)-1]
f) XX[(n-5)-0],0000
g) X0000,X[(n-1)-4]
14. DefineX1X0=00(S0),01(S1),10(S2),11(S3).Iistheinputbit.
X1'X0'I': M0
X1'X0'I: X01,M0
X1'X0I': X00
X1'X0I: X11,X00
X1X0'I': X01,M1
X1X0I': X10,X00,M0
X1X0I: X10,M0
15.
16. DefineX1X0=00(S0),01(S1),10(S2),11(S3).Iistheinputbit.
Bruteforcesolution(oneRTLstatementperinputvalueperstate)
X2'X1'X0'I': M0
X2'X1'X0'I: X01,M0
X2'X1'X0I': X11,X00
X2'X1'X0I: X11,X01
X2'X1X0'I': X21,X10
X2'X1X0'I: X21,X10,X01
X2'X1X0I': X21,X00,M1
X2'X1X0I: X21
X2X1'X0'I': X20
X2X1'X0'I: X20,X01
X2X1'X0I': X20,X11,X00
X2X1'X0I: X20,X11
X2X1X0'I': X10,M0
X2X1X0'I: X10,X01,M0
X2X1X0I': X00
Simplersolution(oneRTLstatementperstate)
X2'X1'X0': X0I,M0
X2'X1'X0: X11,X0I
X2'X1X0': X21,X10,X0I
X2'X1X0: X21,X0I,MI'
X2X1'X0': X20,X0I
X2X1'X0: X20,X11,X0I
X2X1X0': X10,X0I,M0
X2X1X0: X0I,MI'
Simplestsolution(combiningstates)
1: X2X1,X1X0,X0I
X2'X1'X0'+X2'X1X0I'+X2X1X0': MX2'X1X0I'
17.
18. libraryIEEE;
useIEEE.std_logic_1164.all;
entitystring_checkeris
port(
I,clk:instd_logic;
M:outstd_logic
);
endstring_checker;
architecturea_string_checkerofstring_checkeris
typestatesis(S0,S1,S2,S3);
signalpresent_state,next_state:states;
begin
state_check_string:process(present_state,I)
begin
casepresent_stateis
whenS0=>M<='0';
if(I='0')thennext_state<=S0;
elsenext_state<=S1;
endif;
whenS1=>M<='0';
if(I='0')thennext_state<=S0;
elsenext_state<=S2;
endif;
whenS2=>M<='0';
if(I='0')thennext_state<=S3;
elsenext_state<=S2;
endif;
whenS3=>M<='1';
if(I='0')thennext_state<=S0;
elsenext_state<=S1;
endif;
endcase;
endprocessstate_check_string;
state_transition:process(clk)
begin
ifrising_edge(clk)thenpresent_state<=next_state;
endif;
endprocessstate_transition;
enda_string_checker;
19. libraryIEEE;
useIEEE.std_logic_1164.all;
entitystring_checkeris
port(
I,clk:instd_logic;
X1,X0:bufferstd_logic;
M:outstd_logic
);
endstring_checker;
architecturea_string_checkerofstring_checkeris
begin
cct_string_checker:process(X1,X0,I,clk)
begin
ifrising_edge(clk)then
X1<=(X1and(notX0))or
((notX1)andX0andI);
X0<=((notX1)and(notX0)andI)or
(X1and(notX0)and(notI))or
(X1andX0andI);
endif;
M<=X1ANDX0;
endprocesscct_string_checker;
enda_string_checker;
20. libraryIEEE;
useIEEE.std_logic_1164.all;
entitystring_checkeris
port(
I,clk:instd_logic;
M:outstd_logic
);
endstring_checker;
architecturea_string_checkerofstring_checkeris
typestatesis(S0,S1,S2,S3,S4,S5,S6,S7);
signalpresent_state,next_state:states;
begin
state_check_string:process(present_state,I)
begin
casepresent_stateis
whenS0=>M<='0';
if(I='0')thennext_state<=S0;
elsenext_state<=S1;
endif;
whenS1=>M<='0';
if(I='0')thennext_state<=S2;
elsenext_state<=S3;
endif;
whenS2=>M<='0';
if(I='0')thennext_state<=S4;
elsenext_state<=S5;
endif;
whenS3=>M<='0';
if(I='0')thennext_state<=S6;
elsenext_state<=S7;
endif;
whenS4=>M<='0';
if(I='0')thennext_state<=S0;
elsenext_state<=S1;
endif;
whenS5=>M<='0';
if(I='0')thennext_state<=S2;
elsenext_state<=S3;
endif;
whenS6=>M<='1';
if(I='0')thennext_state<=S4;
elsenext_state<=S5;
endif;
whenS7=>M<='0';
if(I='0')thennext_state<=S6;
elsenext_state<=S7;
endif;
endcase;
endprocessstate_check_string;
state_transition:process(clk)
begin
ifrising_edge(clk)thenpresent_state<=next_state;
endif;
endprocessstate_transition;
enda_string_checker;
21. libraryIEEE;
useIEEE.std_logic_1164.all;
entitystring_checkeris
port(
I,clk:instd_logic;
X2,X1,X0:bufferstd_logic;
M:outstd_logic
);
endstring_checker;
architecturea_string_checkerofstring_checkeris
begin
cct_string_checker:process(X1,X0,I,clk)
begin
ifrising_edge(clk)then
X2<=X1;
X1<=X0;
X0<=I;
endif;
M<=X2andX1and(notX0);
endprocesscct_string_checker;
enda_string_checker;
22. libraryIEEE;
useIEEE.std_logic_1164.all;
entitytoll_booth_controlleris
port(
I1,I0,C,clk:instd_logic;
R,G,A:outstd_logic
);
endtoll_booth_controller;
architecturea_toll_booth_controlleroftoll_booth_controlleris
typestatesis(SN,S0,S5,S10,S15,S20,S25,S30,SP,SC);
signalpresent_state,next_state:states;
begin
state_toll_booth_controller:process(present_state,I1,I0)
begin
casepresent_stateis
whenSN=>R<='1';G<='0';A<='0';
if(C='1')thennext_state<=S0;
elsenext_state<=SN;
endif;
whenS0=>R<='1';G<='0';A<='0';
if(C='0')thennext_state<=SC;
elsif(I1='0'ANDI0='1')thennext_state<=S5;
elsif(I1='1'ANDI0='0')thennext_state<=S10;
elsif(I1='1'ANDI0='1')thennext_state<=S25;
elsenext_state<=S0;
endif;
whenS5=>R<='1';G<='0';A<='0';
if(C='0')thennext_state<=SC;
elsif(I1='0'ANDI0='1')thennext_state<=S10;
elsif(I1='1'ANDI0='0')thennext_state<=S15;
elsif(I1='1'ANDI0='1')thennext_state<=S30;
elsenext_state<=S5;
endif;
whenS10=>R<='1';G<='0';A<='0';
if(C='0')thennext_state<=SC;
elsif(I1='0'ANDI0='1')thennext_state<=S15;
elsif(I1='1'ANDI0='0')thennext_state<=S20;
elsif(I1='1'ANDI0='1')thennext_state<=SP;
elsenext_state<=S10;
endif;
whenS15=>R<='1';G<='0';A<='0';
if(C='0')thennext_state<=SC;
elsif(I1='0'ANDI0='1')then
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