计算机组成与结构体系英文课件：Chapter-3-–-Basic-InputOutput

ComputerOrganization&Architecture

Chapter3–BasicInput/OutputContentofthislecture3.1AccessingI/ODevices3.2Interrupts8.4DirectMemoryAccessSummaryAccessingI/ODevices(1)I/ODevicesLinktotheoutsideworldTypesHumanreadableMonitorPrinterMachinereadableDiskCDROMScannerCommunicationModemNetworkInterfaceCard(NIC)AccessingI/ODevices(2)ExamplesofI/ODevicesDevice Input/Output DateRate(Kbytes/s)Keyboard Input 0.01Mouse Input 0.02Voiceinput(microphone)Input 0.02Scanner Input 200Voiceoutput(speaker) Output 0.5Dot-matrixprinter Output 1Laserprinter Output 100Graphicsdisplay Output 30,000Localareanetwork Input/output 200–20,000Opticaldisk Storage(I/O) 500Magnetictape Storage(I/O) 2,000Magneticdisk Storage(I/O) 2,000AccessingI/ODevices(3)AccessingI/ODevices(4)AccessingI/ODevices(ctd.)AccessingI/ODevices(5)AccessingI/ODevices(6)I/ODeviceInterfaceTheaddressdecoder,thedataandstatusregisters,andthecontrolcircuitryconstitutethedevice’sinterfacecircuit.AccessingI/ODevices(7)I/OInterface(ctd.)FunctionsofinterfaceDevicecommunicationControl:DeterminewhetherdevicewillsendorreceivedataData:ActualdatatransferredStatus:Deviceisready,DataisavailablefortransferorerrorDatabufferingMusthandlevaryingdataratesfrommemoryandI/OdeviceBufferdatasothatnoonegetstieddownErrordetectionReporttoCPUmechanicalfailuree.g.paperjamReportdatatransmissionerrorAccessingI/ODevices(8)I/OInterface(ctd.)Functionsofinterface(ctd.)ControlandSignalingCo-ordinatesdatatransferbasedoncommunicationmethodwiththeprocessorCommunicationwithCPUProgrammeda.k.aPollingInterruptdrivenDirectMemoryAccess(DMA)AccessingI/ODevices(9)AddressingModesofI/ODevices(Interface)Memory-mappedI/OI/Odevicesandthememorysharethesameaddressspace.Somememoryaddressvaluesareusedtorefertoperipheraldeviceinterfaceregisters.I/Olooksjustlikememoryread/writeExample

LoadR2,DATAINDATAINistheaddressoftheinputbufferassociatedwiththekeyboard.AdvantageAnymachineinstructionthatcanaccessmemorycanbeusedtotransferdatatoorfromanI/Odevice.AccessingI/ODevices(10)AddressingModesofI/ODevices(Interface)(ctd.)Memory-mappedI/O(ctd.)DisadvantageValuablememoryaddressspaceisusedup.IsolatedI/OUsespecialInandOutinstructionstoperformI/Otransfers.AdvantageI/Odevicesdealwithfewaddresslines.NoteAseparateI/OaddressspacedoesnotnecessarilymeanthattheI/Oaddresslinesarephysicallyseparatefromthememoryaddresslines.AccessingI/ODevices(11)Program-controlledI/OCPUexecutesaprogramthatcommunicateswithI/OmoduleRead/writecommandsSensingstatusTransferringdataCPUwaitsforI/OmoduletocompleteoperationDisadvantageisthatitwastesCPUtimeExample:Considerataskthatreadscharacterstypedonakeyboard,storesthesedatainthememory,anddisplaysthesamecharactersonadisplayscreen.AccessingI/ODevices(12)Program-controlledI/O(ctd.)Example(ctd.)ThedifferenceinspeedbetweentheprocessorandI/Odevicescreatestheneedformechanismstosynchronizethetransferofdatabetweenthem.Onoutput,theprocessorsendsthefirstcharacterandthenwaitsforasignalfromthedisplaythatthecharacterhasbeenreceived.Itthensendsthesecondcharacter,andsoon.Oninput,theprocessorwaitsforasignalindicatingthatacharacterkeyhasbeenstruckandthatitscodeisavailableinsomebufferregisterassociatedwiththekeyboard.Thentheprocessorproceedstoreadthatcode.AccessingI/ODevices(13)Program-controlledI/O(ctd.)Example(ctd.)SignalingProtocolforI/ODevicesAssumethattheI/Odeviceshaveawaytosenda‘ready’signaltotheprocessorForkeyboard,indicatescharactercanberead

soprocessorusesLoadtoaccessdataregisterFordisplay,indicatescharactercanbesentsoprocessorusesStoretoaccessdataregisterThe‘ready’signalineachcaseisastatusflag

instatusregisterthatispolledbyprocessorAccessingI/ODevices(14)AccessingI/ODevices(15)Program-controlledI/O(ctd.)Example(ctd.)Keyboard&DisplayInterfaceRegisterOrganizationAccessingI/ODevices(16)Program-controlledI/O(ctd.)Example(ctd.)WaitLoopforPollingI/OStatusProgram-controlledI/Oimplementedwithawaitloopforpollingkeyboardstatusregister:

READWAIT: LoadByte R4,KBD_STATUS

And R4,R4,#2

Branch_if_[R4]0READWAIT

LoadByte R5,KBD_DATAKeyboardcircuitplacescharacterinKBD_DATAandsetsKINflaginKBD_STATUSCircuitclearsKINflagwhenKBD_STATUSreadAccessingI/ODevices(17)Program-controlledI/O(ctd.)Example(ctd.)WaitLoopforPollingI/OStatusSimilarwaitloopfordisplaydevice:

WRITEWAIT: LoadByte R4,DISP_STATUS

And R4,R4,#4

Branch_if_[R4]0WRITEWAIT

StoreByte R5,DISP_DATADisplaycircuitsetsDOUTflaginDISP_STATUSafterpreviouscharacterhasbeendisplayedCircuitautomaticallyclearsDOUTflag

whenDISP_STATUSregisterisreadAccessingI/ODevices(18)AccessingI/ODevices(19)Program-controlledI/O(ctd.)Example(ctd.)RISCProgramRISC-andCISC-styleI/OProgramsAccessingI/ODevices(20)Program-controlledI/O(ctd.)Example(ctd.)CISCProgramRISC-andCISC-styleI/OProgramsInterrupts(1)WhatisInterrupt?Aninterruptisaneventthatcausestheprocessortostopitscurrentprogramexecutionandswitchtoperforminganinterruptserviceroutine.AdvantagesofInterruptOvercomesCPUwaitingNorepeatedCPUcheckingofdeviceI/OmoduleinterruptswhenreadyInterrupts(2)Interrupts(3)Interrupts(4)Example3.1(ctd.)Interrupts(5)ConceptsofInterruptInterruptRequestSignalAsignalthatanI/Odevicesendstotheprocessorthroughoneofthebuscontrollines.InterruptAcknowledgeSignalTheCPUissuethesignaltoacknowledgestheinterruptInterrupts(6)ConceptsofInterrupt(ctd.)Interrupt-ServiceRoutine(InterruptHandler)Theroutineexecutedinresponsetoaninterruptrequestiscalledtheinterrupt-serviceroutine.InterruptLatencyThedelaybetweenthetimeaninterruptrequestisreceivedandthestartofexecutionoftheinterrupt-serviceroutine.Interrupts(7)ConceptsofInterrupt(ctd.)Differencebetweensubroutineandinterrupt-serviceroutineAsubroutineperformsafunctionrequiredbytheprogramfromwhichitiscalled.Assuch,potentialchangestostatusinformationandcontentsofregistersareanticipated.Aninterrupt-serviceroutinemaynothaveanyrelationtotheportionoftheprogrambeingexecutedatthetimetheinterruptrequestisreceived.Therefore,beforestartingexecutionoftheinterruptserviceroutine,statusinformationandcontentsofprocessorregistersthatmaybealteredinunanticipatedwaysduringtheexecutionofthatroutinemustbesaved.Thissavedinformationmustberestoredbeforeexecutionoftheinterruptedprogramisresumed.Interrupts(8)InterruptProcessingWhenaninterruptoccurs(andisaccepted),theexecutionofthecurrentprogramissuspendedMustsavePC,RegistersinProcessControlBlock(PCB)InterruptserviceroutineexecutestoservicetheinterruptFlowchart(nextpage)Interrupts(9)InterruptProcessing(ctd.)Interrupts(10)EnablingandDisablingInterruptsEnablinganddisablinginterruptsarefundamentaltoallcomputersTheinterruptionofprogramexecutionmustbecarefullycontrolledbecauseinterruptscanarriveatanytime,theymayalterthesequenceofeventsfromthatenvisagedbytheprogrammer.Itmaybenecessarytoguaranteethataparticularsequenceofinstructionsisexecutedtotheendwithoutinterruptionbecausetheinterruptserviceroutinemaychangesomeofthedatausedbytheinstructionsinquestion.Interrupts(11)EnablingandDisablingInterrupts(ctd.)InterruptControlatProcessorEndSetInterrupt-enablebitintheProgramStatusregisterSuitableforasimpleprocessorwithonlyoneinterrupt-requestline.Havetheprocessorautomaticallydisableinterrupts(cleartheInterrupt-enablebit)beforestartingtheexecutionoftheinterrupt-serviceroutine.(IE=0)WhenaReturn-from-interruptinstructionisexecuted,thecontentsofthePSarerestoredfromthestack,settingtheInterrupt-enablebitbackto1.(IE=1)Interrupts(12)EnablingandDisablingInterrupts(ctd.)InterruptControlatI/ODeviceEndItisimportanttoensurethatinterruptrequestsaregeneratedonlybythoseI/Odevicesthattheprocessoriscurrentlywillingtorecognize.Needamechanismintheinterfacecircuitsofindividualdevicestocontrolwhetheradeviceisallowedtointerrupttheprocessor.Aninterrupt-enablebitinacontrolregisterdetermineswhetherthedeviceisallowedtogenerateaninterruptrequest.Interrupts(13)EnablingandDisablingInterrupts(ctd.)InterruptControlatI/ODeviceEnd(ctd.)Interrupts(14)MultipleDevicesInterruptSystemDesignIssuesHowdoyouidentifythemoduleissuingtheinterrupt?Howtheprocessorobtainthestartingaddressoftheappropriateroutineofdifferentdevices?—IdentifyInterruptSourceShouldadevicebeallowedtointerrupttheprocessorwhileanotherinterruptisbeingserviced?—Multi-levelInterruptHowshouldtwoormoresimultaneousinterruptrequestsbehandled?—SimultaneousInterruptInterrupts(15)Interrupts(16)IdentifyInterruptSource(ctd.)CommonInterrupt-requestLine(ctd.)Polling(NonvectoredInterrupt)(ctd.)Interrupts(17)IdentifyInterruptSource(ctd.)

CommonInterrupt-requestLine(ctd.)VectoredInterruptAninterruptschemewheretheinterruptingdeviceidentifiesitselfwhengeneratinginterrupts.InterruptVectorAninterruptvectoristhememoryaddressofaninterrupthandler,oranindexintoanarraycalledaninterruptvectortableordispatch

table.Interruptvectortablescontainthememoryaddressesofinterrupthandlers.Interrupts(18)IdentifyInterruptSource(ctd.)

CommonInterrupt-requestLine(ctd.)VectoredInterrupt(ctd.)

Whenadevicesendsaninterruptrequest,theprocessormaynotreadytoreceivetheinterrupt-vectorcodeimmediately.Whentheprocessorisreadytoreceivetheinterrupt-vectorcode,itactivatestheinterrupt-acknowledgeline,INTATheI/Odevicerespondsbysendingitsinterrupt-vectorcodeandturningofftheINTRsignal.Interrupts(19)Multi-levelInterrupt

Single-levelInterruptWhetheronedeviceorseveralI/Odevices,interruptsshouldbedisabledduringtheexecutionofaninterrupt-serviceroutine.Multi-levelInterrupt(InterruptNesting)Itisnecessarytoacceptanotherdeviceinterruptduringtheexecutionofaninterrupt-serviceroutineforadevice.I/Odevicesareorganizedinaprioritystructure.Aninterruptrequestfromahigh-prioritydeviceshouldbeacceptedwhiletheprocessorisservinganotherrequestfromalower-prioritydevice.Interrupts(20)Multi-levelInterrupt(ctd.)MultipleInterrupt(ctd.)Multi-LevelPriorityAssignapriorityleveltotheprocessorthatcanbechangedunderprogram(privilegedinstructions)control.Thepriorityleveloftheprocessoristhepriorityoftheprogramthatiscurrentlybeingexecuted.Theprocessoracceptsinterruptsonlyfromdevicesthathaveprioritieshigherthanitsown.Atthetimetheexecutionofaninterrupt-serviceroutineforsomedeviceisstarted,thepriorityoftheprocessorisraisedtothatofthedevice.

Theprocessor’sprioritycanbeencodedinafewbitsoftheprocessorstatusregister.Interrupts(21)Multi-levelInterrupt(ctd.)Multi-levelInterrupt(ctd.)Multi-LevelPriority(ctd.)Implementationofinterruptpriorityusingindividualinterrupt-requestandacknowledgelinesInterrupts(22)SimultaneousInterruptIndividualdevicehasindividualinterrupt-requestandacknowledgelinesTheprocessorsimplyacceptstherequesthavingthehighestpriority.Itallowstheprocessortoacceptinterruptrequestsfromsomedevicesbutnotfromothers,dependingupontheirpriorities.Severaldevicesshareoneinterrupt-requestlineSoftwarePollDaisyChain(HardwarePoll)PriorityGroupInterrupts(23)SimultaneousInterrupt(ctd.)SoftwarePollTheprocessorpollthestatusregisteroftheI/Odevice.Priorityisdeterminedbytheorderinwhichthedevicesarepolled.DaisyChainInthedaisychainarrangement,thedevicethatiselectricallyclosesttotheprocessorhasthehighestpriority.Theseconddevicealongthechainhassecondhighestpriority,andsoon.ProcessorDevice2INTRINTADevicenDevice1Interrupts(24)SimultaneousInterrupt(ctd.)PriorityGroupcircuitDeviceDevicePriorityarbitrationProcessorDeviceDeviceINTR1INTRpINTA1INTApInterrupts(25)ProcessorControlRegistersProcessorStatusRegister(PS)IPSregisteriswherePSisautomaticallysavedwhenaninterruptrequestisrecognizedIENABLEregisterallowstheprocessortoselectivelyrespondtoindividualI/Odevices.HasonebitperdeviceIPENDINGhasonebitperdevicetoindicateifinterruptrequesthasnotyetbeenservicedInterrupts(26)ProcessorControlRegisters(ctd.)Interrupts(27)ProcessorControlRegisters(ctd.)AccessingControlRegistersUsespecialMoveinstructionsthattransfervaluestoandfromgeneral-purposeregistersTransferpendinginterruptrequeststoR4:

MoveControl R4,IPENDINGTransfercurrentprocessorIEsettingtoR2:

MoveControl R2,PSTransferdesiredbitpatterninR3toIENABLE:

MoveControl IENABLE,R3Interrupts(28)ExamplesofInterruptProgramsExample3.2Letusconsideragainthetaskofreadingalineofcharacterstypedonakeyboard,storingthecharactersinthemainmemory,anddisplayingthemonadisplaydevice.Now,wewilluseinterruptswiththekeyboard,butpollingwiththedisplay.Assumethataspecificmemorylocation,ILOC,isdedicatedfordealingwithinterrupts,andthatitcontainsthefirstinstructionoftheinterrupt-serviceroutine.Interrupts(29)ExamplesofInterruptPrograms(ctd.)Example3.2(ctd.)Wheneveraninterruptrequestarrivesattheprocessor,andprocessorinterruptsareenabled,theprocessorwillautomatically:Savethecontentsoftheprogramcounter,eitherinaprocessorregisterthatholdsthereturnaddressorontheprocessorstack.SavethecontentsofthestatusregisterPSbytransferringthemintotheIPSregister,andcleartheIEbitinthePS.LoadtheaddressILOCintotheprogramcounterInterrupts(30)ExamplesofInterruptPrograms(ctd.)Interrupts(31)ExamplesofInterruptPrograms(ctd.)Interrupts(32)ExamplesofInterruptPrograms(ctd.)Example3.3Supposeaprogramneedstodisplayapageoftextstoredinthememory.Thiscanbedonebyhavingtheprocessorsendacharacterwheneverthedisplayinterfaceisready,whichmaybeindicatedbyaninterruptrequest.Assumethatboththedisplayandthekeyboardareusedbythisprogram,andthatbothareenabledtoraiseinterruptrequests.Interrupts(33)ExamplesofInterruptPrograms(ctd.)Example3.3(ctd.)Touseinterruptsforbothkeyboard&display,callsubroutinesfromILOCserviceroutineServiceroutinereadsIPENDINGregisterCheckswhichdevicebit(s)is(are)set

todeterminewhichsubroutine(s)tocallServiceroutinemustsave/restoreLinkregisterAlsoneedseparatepointervariabletoindicate

outputcharacterfornextdisplayinterruptInterrupts(34)ExamplesofInterruptPrograms(ctd.)DirectMemoryAccess(1)InterruptdrivenandprogrammedI/OrequireactiveCPUinterventionTransferrateislimitedCPUistiedupSolution:DMAUsedforhigh-speedblocktransfersbetweenadeviceandmemoryDuringthetransfer,theCPUisnotinvolvedTypicalDMAdevices:Diskdrives,tapedrivesRememberKeyboarddatarate

0.01KB/s(1byteevery100ms)Diskdrivedatarate2,000KB/s(1byteevery0.5µs)TransferrateistoohightobecontrolledbysoftwareexecutingontheCPUDirectMemoryAccess(2)DMAOperation1.TheCPU“prepares”theDMAoperationbytransferringinformationtoaDMAcontroller(DMAC):LocationofthedataonthedeviceLocationofthedatainmemorySizeoftheblocktotransferDirectionofthetransferModeoftransfer(burst,cyclestealing,transparent)2.Whenthedeviceisreadytotransferdata,theDMACtakescontrolofthesystembuses(DMAcontrollerdealswithtransfer)3.DMACsendsinterruptwhenfinishedDirectMemoryAccess(3)DMAOperation(ctd.)DatabusAddressbusControlbusMemoryDMACCPUDiskTheCPU“prepares”theDMACProgram-controlledI/ODirectMemoryAccess(4)DMAOperation(ctd.)DatabusAddressbus