计算机组成原理教学课件：4-The-processor

Computer

Organization&Design

—TheHardware/SoftwareInterface2026/5/41TheprocessorChapterFour:Theprocessor4.1Introduction4.2LogicDesignConventions4.3Buildingadatapath4.4ASimpleImplementationScheme4.5AnOverviewofPipelining4.6PipelinedDatapathandControl4.7DataHazards:ForwardingversusStalling4.8ControlHazards4.9Exceptions4.10ParallelismandAdvancedInstruction-LevelParallelism4.11RealStuff:theAMDOpteronX4Pipeline2026/5/42We‘lllookatanimplementationoftheMIPSSimplifiedtocontainonly:memory-referenceinstructions:lw,swarithmetic-logicalinstructions:add,sub,and,or,sltcontrolflowinstructions:beq,jAnOverviewoftheimplementationForeveryinstruction,thefirsttwostepareidenticalFetchtheinstructionfromthememoryDecodeandreadtheregistersNextstepsdependontheinstructionclassMemory-referenceArithmetic-logical branches4.1IntroductionWhataresteps?HowmanyFUN.?2026/5/43We'rereadytolookatanimplementationoftheMIPSinstructionsetSimplifiedtocontainonlyarithmetic-logicinstructions:add,sub,and,or,sltmemory-referenceinstructions:lw,swcontrol-flowinstructions:beq,jImplementingMIPSoprsrtoffset6bits5bits5bits16bitsoprsrtrdfunctshamt6bits5bits5bits5bits5bits6bitsR-FormatI-Formatopaddress6bits26bitsJ-FormatImplementingMIPS:theFetch/ExecuteCycleAnabstractviewoftheimplementationofMIPS2026/5/46Overview:ProcessorImplementationStylesSingleCycleperformeachinstructionin1clockcycleclockcyclemustbelongenoughforslowestinstruction;therefore,disadvantage:onlyasfastasslowestinstructionMulti-Cyclebreakfetch/executecycleintomultiplestepsperform1stepineachclockcycleadvantage:eachinstructionusesonlyasmanycyclesasitneedsPipelinedexecuteeachinstructioninmultiplestepsperform1step/instructionineachclockcycleprocessmultipleinstructionsinparallel–assemblylineChapterFour:Theprocessor4.1Introduction4.2LogicDesignConventions4.3Buildingadatapath4.4ASimpleImplementationScheme4.5AnOverviewofPipelining4.6PipelinedDatapathandControl4.7DataHazards:ForwardingversusStalling4.8ControlHazards4.9Exceptions4.10ParallelismandAdvancedInstruction-LevelParallelism4.11RealStuff:theAMDOpteronX4Pipeline2026/5/48Twotypesoffunctionalelementsinthehardware:elementsthatoperateondata(calledcombinationalelements)elementsthatcontaindata(calledstateorsequentialelements)FunctionalElementsCombinationalElementsWorksasaninput

outputfunction,e.g.,ALUCombinationallogicreadsinputdatafromoneregisterandwritesoutputdatatoanother,orsame,registerread/writehappensinasinglecycle–combinationalelementcannotstoredatafromonecycletoafutureoneCombinationallogichardwareunitsStateElementsStateelementscontaindataininternalstorage,e.g.,registersandmemoryAllstateelementstogetherdefinethestateofthemachineWhatdoesthismean?

Thinkofshuttingdownandstartingupagain…Flipflopsandlatchesare1-bitstateelements,equivalently,theyare1-bitmemoriesTheoutput(s)ofaflipfloporlatchalwaysdependsonthebitvaluestored,i.e.,itsstate,andcanbecalled1/0orhigh/lowortrue/falseTheinputtoaflipfloporlatchcanchangeitsstatedependingonwhetheritisclockedornot…Set-Reset(SR-)latch

(unclocked)QQbarSbar(set)Rbar(reset)n1n2equivalentlywithnorgatesThinkofSbarasS,theinverseofset(whichsetsQto1),andRbarasR,theinverseofreset.Aset-resetlatchmadefromtwocross-couplednandgatesisabasicmemoryunit.

WhenbothSbarandRbarare1,theneitheroneofthefollowing

twostatesisstable:Q=1&Qbar=0Q=0&Qbar=1andthelatchwillcontinueinthecurrentstablestate.IfSbarchangesto0(whileRbarremainsat1),thenthelatchisforcedtotheexactly

onepossiblestablestate(a).IfRbarchangesto0(whileSbarremainsat1),thelatchisforcedtotheexactlyonepossiblestablestate(b).So,thelatchrememberswhichofSbarorRbarwaslast0duringthetimetheyareboth1.WhenbothSbarandRbarare0theexactlyonestablestateisQ=Qbar=1.However,ifafterthatbothSbarandRbarreturnto1,thelatchmustthenjump

non-deterministicallytooneofstablestates(a)or(b),whichisundesirablebehavior.Clocksareusedinsynchronouslogictodeterminewhenastateelementistobeupdatedinlevel-triggeredclockingmethodologyeitherthestatechangesonlywhentheclockishighoronlywhenitislow(technology-dependent)inedge-triggeredclockingmethodologyeithertherisingedgeorfallingedgeisactive(dependingontechnology)–i.e.,stateschangeonlyonrisingedgesoronlyonfallingedgeLatches

arelevel-triggeredFlipflops

areedge-triggeredSynchronousLogic:

ClockedLatchesandFlipflopsClockedSR-latchStatecanchangeonlywhenclockishighPotential

problem:bothinputsSbar=0&Rbar=0willcausenon-deterministicbehaviorQQbarn1n2SbarclkRbarr2r1aclkbarYXStatecanchangeonlywhenclockishighOnlysingledatainput(compareSR-latch)Noproblemwithnon-deterministicbehaviorClockedD-latchTimingdiagramofD-latchDQQbarn1n2clkr2r1a1a2clkbarXYDbarClockedD-flipflopNegativeedge-triggeredMadefromthreeSR-latchessbarsrqqbarrbarclearclkcbardclkbarRegistersareimplementedwitharraysofD-flipflopsStateElementsontheDatapath:RegisterFileRegisterfilewithtworeadportsandonewriteportClock5bits5bits5bits32bits32bits32bitsControlsignalReadRegisterFile----BuiltusingDflip-flops5bits5bits5bits32bits32bits32bits2026/5/418RegisterFilewrite32bitsrdorrt5bitsWritesignals2026/5/419Single-cycleImplementationofMIPSOurfirstimplementationofMIPSwilluseasinglelongclockcycleforeveryinstructionEveryinstructionbeginsononeup(or,down)clockedgeandendsonthenextup(or,down)clockedgeThisapproachisnotpracticalasitismuchslowerthanamulticycleimplementationwheredifferentinstructionclassescantakedifferentnumbersofcyclesinasingle-cycleimplementationeveryinstructionmusttakethesameamountoftimeastheslowestinstructioninamulticycleimplementationthisproblemisavoidedbyallowingquickerinstructionstousefewercyclesEventhoughthesingle-cycleapproachisnotpracticalitissimpleandusefultounderstandfirstNote:weshallimplementjumpattheveryendDatapath:InstructionStore/Fetch&PCIncrement

ThreeelementsusedtostoreandfetchinstructionsandincrementthePCDatapathAnimatingtheDatapathInstruction<-MEM[PC]PC<-PC+4Datapath:R-TypeInstructionTwoelementsusedtoimplementR-typeinstructionsDatapathAnimatingtheDatapathaddrd,rs,rtR[rd]<-R[rs]+R[rt];Datapath:

Load/StoreInstructionTwoadditionalelementsusedToimplementload/storesDatapathAnimatingtheDatapathlwrt,offset(rs)R[rt]<-MEM[R[rs]+s_extend(offset)];AnimatingtheDatapathswrt,offset(rs)MEM[R[rs]+sign_extend(offset)]<-R[rt]Datapath:BranchInstructionDatapathNoshifthardwarerequired:simplyconnectwiresfrominputtooutput,eachshiftedleft2bitsAnimatingtheDatapathbeqrs,rt,offsetif(R[rs]==R[rt])then

PC<-PC+4+s_extend(offset<<2)MIPSDatapathI:Single-CycleInputiseitherregister(R-type)orsign-extendedlowerhalfofinstruction(load/store)CombiningthedatapathsforR-typeinstructionsandload/storesusingtwomultiplexorsDataiseitherfromALU(R-type)ormemory(load)AnimatingtheDatapath:

R-typeInstructionaddrd,rs,rtAnimatingtheDatapath:

LoadInstructionlwrt,offset(rs)AnimatingtheDatapath:

StoreInstructionswrt,offset(rs)MIPSDatapathII:Single-CycleAddinginstructionfetchSeparateinstructionmemoryasinstructionanddatareadoccurinthesameclockcycleSeparateadderasALUoperationsandPCincrementoccurinthesameclockcycleMIPSDatapathIII:Single-CycleAddingbranchcapabilityandanothermultiplexorInstructionaddressiseitherPC+4orbranchtargetaddressExtraadderneededasbothaddersoperateineachcycleNewmultiplexorDatapathExecutingaddaddrd,rs,rtDatapathExecutinglwlwrt,offset(rs)DatapathExecutingswswrt,offset(rs)DatapathExecutingbeqbeqr1,r2,offsetControlControlunittakesinputfromtheinstructionopcodebitsControlunitgeneratesALUcontrolinputwriteenable(possibly,readenablealso)signalsforeachstorageelementselectorcontrolsforeachmultiplexorALUControlPlantocontrolALU:maincontrolsendsa2-bitALUOpcontrolfieldtotheALUcontrol.BasedonALUOpandfunctfieldofinstructiontheALUcontrolgeneratesthe3-bitALUcontrolfieldALUcontrolFunc-field

tion

000and001or010add110sub111sltALUmustperformaddforload/stores(ALUOp00)subforbranches(ALUOp01)oneofand,or,add,sub,sltforR-typeinstructions,dependingontheinstruction’s6-bitfunctfield(ALUOp10)

MainControlALUControl2ALUOp6Instructionfunctfield3ALUcontrolinputToALUALUOpgenerationbymaincontrolRecallfromCh.4Mustdescribehardwaretocompute3-bitALUconrolinputDesigningtheALUdecoder(Secondlevel)InstructionopcodeALUOpInstructionoperationFunctfieldDesiredALUactionALUcontrolInputLW00LoadwordxxxxxxLoadword0010SW00StorewordxxxxxxStoreword0010Beq01branchequalxxxxxxbranchequal0110R-type10add100000add0010R-type10subtract100010subtract0110R-type10AND100100AND0000R-type10OR100101OR0001R-type10Setonlessthan101010Setonlessthan01112026/5/442Describeitusingatruthtable(canturnintogates):TruthTableforALUdecoder2026/5/443TheALUcontrolsignals----logiccircuit0xx100xxxxxxxxx1F1F0F3F2F11xx100xXxxxX1xx1F1F0F3F2F20xx001xXxxxXxxx1F1F0F3F2F0F32026/5/444DesigningtheMainControlUnit

(Firstlevel)MainControlUnitfunctionALUop(2)Divided7controlsignalsinto2groups4Mux3R/WMaincontrolInstructionopcode(6)ALUop(2)Mux(4)R/W(3)2026/5/445DesigningtheMainControl31-2625-2120-1615-1110-65-031-2625-2120-1615-0opcodeopcodersrsrtrtaddressrdshamtfunctR-typeLoad/storeorbranchDatapathwithControlIAddingcontroltotheMIPSDatapathIII(andanewmultiplexortoselectfieldtospecifydestinationregister):whatarethefunctionsofthe9controlsignals?NewmultiplexorControlSignalsSignalNameEffectwhendeassertedEffectwhenassertedRegDstTheregisterdestinationnumberfortheTheregisterdestinationnumberfortheWriteregistercomesfromthertfield(bits20-16)Writeregistercomesfromtherdfield(bits15-11)RegWriteNoneTheregisterontheWriteregisterinputiswritten withthevalueontheWritedatainputAlLUSrcThesecondALUoperandcomesfromtheThesecondALUoperandisthesign-extended,secondregisterfileoutput(Readdata2)lower16bitsoftheinstructionPCSrcThePCisreplacedbytheoutputoftheadderThePCisreplacedbytheoutputoftheadder thatcomputesthevalueofPC+4thatcomputesthebranchtargetMemReadNone Datamemorycontentsdesignatedbytheaddress inputareputonthefirstReaddataoutputMemWriteNone Datamemorycontentsdesignatedbytheaddress inputarereplacedbythevalueoftheWritedatainputMemtoRegThevaluefedtotheregisterWritedatainput ThevaluefedtotheregisterWritedatainputcomesfromtheALU comesfromthedatamemoryEffectsofthesevencontrolsignals

DatapathwithControlII

MIPSdatapathwiththecontrolunit:inputtocontrolisthe6-bitinstructionopcodefield,outputisseven1-bitsignalsandthe2-bitALUOpsignalDatapathwith

ControlII(cont.)DeterminingcontrolsignalsfortheMIPSdatapathbasedoninstructionopcodeControlSignals:

R-TypeInstructionControlsignalsshowninblue10001???Valuedependsonfunct00ControlSignals:

lwInstruction0Controlsignalsshowninblue001011101ControlSignals:

swInstruction0ControlsignalsshowninblueX0101X010ControlSignals:

beqInstructionControlsignalsshowninblueX1100X0001ifZero=1R-typeInstruction:Step1

add$t1,$t2,$t3(active=bold)FetchinstructionandincrementPCcount

R-typeInstruction:Step2

add$t1,$t2,$t3(active=bold)ReadtwosourceregistersfromtheregisterfileR-typeInstruction:Step3

add$t1,$t2,$t3(active=bold)ALUoperatesonthetworegisteroperandsR-typeInstruction:Step4

add$t1,$t2,$t3(active=bold)WriteresulttoregisterSingle-cycleImplementationNotesThestepsarenotreallydistinctaseachinstructioncompletesinexactlyoneclockcycle–theysimplyindicatethesequenceofdataflowingthroughthedatapathTheoperationofthedatapathduringacycleispurelycombinational–nothingisstoredduringaclockcycleTherefore,themachineisstableinaparticularstateatthestartofacycleandreachesanewstablestateonlyattheendofthecycleFetchinstructionandincrementPCReadbaseregisterfromtheregisterfile:thebaseregister($t2)isgivenbybits25-21oftheinstructionALUcomputessumofvaluereadfromtheregisterfileandthesign-extendedlower16bits(offset)oftheinstructionThesumfromtheALUisusedastheaddressforthedatamemoryThedatafromthememoryunitiswrittenintotheregisterfile:thedestinationregister($t1)isgivenbybits20-16oftheinstructionLoadInstructionSteps

lw$t1,offset($t2)LoadInstruction

lw$t1,offset($t2)FetchinstructionandincrementPCReadtworegister($t1and$t2)fromtheregisterfileALUperformsasubtractonthedatavaluesfromtheregisterfile;thevalueofPC+4isaddedtothesign-extendedlower16bits(offset)oftheinstructionshiftedleftbytwotogivethebranchtargetaddressTheZeroresultfromtheALUisusedtodecidewhichadderresult(fromstep1or3)tostoreinthePCBranchInstructionSteps

beq$t1,$t2,offsetBranchInstruction

beq$t1,$t2,offset

TruthTableforMaindecoder2026/5/464opcodeoutput000000R-format100011lw101011sw000100beq2026/5/465CircuitryofmainControllerSimplecombinationallogic(truthtables)opcodeoutput000000R-format100011lw101011sw000100beqL/S 00beq 01R-type 102026/5/466Implementation:ALUControlBlockALUcontrollogicTruthtableforALUcontrolbitsALUOpFunctfieldOperationALUOp1ALUOp0F5F4F3F2F1F000XXXXXX01001XXXXXX1101XXX00000101XXX00101101XXX01000001XXX01010011XXX1010111Implementation:MainControlBlockInputsOutputsTruthtableformaincontrolsignalsMaincontrolPLA(programmablelogicarray):principleunderlyingPLAsisthatanylogicalexpressioncanbewrittenasasum-of-productsDatapathwithControlIII

31-2625-0opcodeaddressJumpMIPSdatapathextendedtojumps:controlunitgeneratesnewJumpcontrolbitNewmultiplexorwithadditionalcontrolbitJumpComposingjumptargetaddressDatapathExecutingj

AllofthelogiciscombinationalWewaitforeverythingtosettledown,andtherightthingtobedoneALUmightnotproducerightanswer?rightawayweusewritesignalsalongwithclocktodeterminewhentowriteCycletimedeterminedbylengthofthelongestpathOurSimpleControlStructureWeareignoringsomedetailslikesetupandholdtimesInstructionnInstructionn+12026/5/471Register-RegisterTiming:OnecompletecycleRsRtRd32ResultALUctrClkbusWRegWr3232busA32busB555RwRaRb3232-bitRegistersALUClkPCRs,Rt,Rd,Op,FuncClk-to-QALUctrInstructionMemoryAccessTimeOldValueNewValueRegWrOldValueNewValueDelaythroughControlLogicbusA,BRegisterFileAccessTimeOldValueNewValuebusWALUDelayOldValueNewValueOldValueNewValueNewValueOldValueRegisterWriteOccursHereWorstCaseTiming(Load)ClkPCRs,Rt,Rd,Op,FuncClk-to-QALUctrInstructionMemoryAccessTimeOldValueNewValueRegWrOldValueNewValueDelaythroughControlLogicbusARegisterFileAccessTimeOldValueNewValuebusBALUDelayOldValueNewValueOldValueNewValueNewValueOldValueExtOpOldValueNewValueALUSrcOldValueNewValueMemtoRegOldValueNewValueAddressOldValueNewValuebusWOldValueNewDelaythroughExtender&MuxRegisterWriteOccursDataMemoryAccessTimeAssumingfixed-periodclockeveryinstructiondatapathusesoneclockcycleimplies:CPI=1cycletimedeterminedbylengthofthelongestinstructionpath(load)butseveralinstructionscouldruninashorterclockcycle:wasteoftimeconsiderifwehavemorecomplicatedinstructionslikefloatingpoint!resourcesusedmorethanonceinthesamecycleneedtobeduplicatedwasteofhardwareandchiparea

Single-CycleDesignProblems

Example:Fixed-periodclockvs.

variable-periodclockina

single-cycleimplementationConsideramachinewithanadditionalfloatingpointunit.Assumefunctionalunitdelaysasfollowsmemory:2ns.,ALUandadders:2ns.,FPUadd:8ns.,FPUmultiply:16ns.,registerfileaccess(readorwrite):1ns.multiplexors,controlunit,PCaccesses,signextension,wires:nodelayAssumeinstructionmixasfollowsallloadstakesametimeandcomprise31%allstorestakesametimeandcomprise21%R-formatinstructionscomprise27%branchescomprise5%jumpscomprise2%FPaddsandsubtractstakethesametimeandtotallycomprise7%FPmultiplysanddividestakethesametimeandtotallycomprise7%Comparetheperformanceof(a)asingle-cycleimplementationusingafixed-periodclockwith(b)oneusingavariable-periodclockwhereeachinstructionexecutesinoneclockcyclethatisonlyaslongasitneedstobe(notreallypracticalbutpretendit’spossible!)SolutionClockperiodforfixed-periodclock=longestinstructiontime=20ns.Averageclockperiodforvariable-periodclock=8

31%+721%+627%+55%+22%+207%+127%=7.0ns.Therefore,performancevar-period/performancefixed-period=20/7=2.9

InstructionInstr.RegisterALUDataRegisterFPUFPUTotalclassmem.readoper.mem.writeadd/mul/timesubdivns.Loadword212218Storeword21227R-format212016Branch2125Jump22FPmul/div2111620FPadd/sub211812

Fixingtheproblemwithsingle-cycledesigns

Onesolution:avariable-periodclockwithdifferentcycletimesforeachinstructionclassunfeasible,asimplementingavariable-speedclockistechnicallydifficultAnothersolution:useasmallercycletimehavedifferentinstructionstakedifferentnumbersofcyclesbybreakinginstructionsintostepsandfittingeachstepintoonecyclefeasible:multicyleapproach!MulticycleApproachNoteparticularitiesofmulticylevs.single-diagramssinglememoryfordataandinstructionssingleALU,noextraaddersextraregisterstoholddatabetweenclockcycles

MulticycleApproachSingle-cycledatapathMulticycledatapath(high-levelview)MulticycleDatapathBasicmulticycleMIPSdatapathhandlesR-typeinstructionsandload/stores:newinternalregisterinredovals,newmultiplexorsinblueovalsOurgoalistobreakuptheinstructionsintostepssothateachsteptakesoneclockcycletheamountofworktobedoneineachstep/cycleisaboutequaleachcycleusesatmostonceeachmajorfunctionalunitsothatsuchunitsdonothavetobereplicatedfunctionalunitscanbesharedbetweendifferentcycleswithinoneinstructionDataatendofonecycletobeusedinnextmustbestored!!BreakinginstructionsintostepsBreakinginstructionsintostepsWebreakinstructionsintothefollowingpotentialexecutionsteps–notallinstructionsrequireallthesteps–eachsteptakesoneclockcycleInstructionfetchandPCincrement(IF)Instructiondecodeandregisterfetch(ID)Execution,memoryaddresscomputation,orbranchcompletion(EX)MemoryaccessorR-typeinstructioncompletion(MEM)Memoryreadcompletion(WB)EachMIPSinstructiontakesfrom3–5cycles(steps)UsePCtogetinstructionandputitintheinstructionregister.IncrementthePCby4andputtheresultbackinthePC.CanbedescribedsuccinctlyusingRTL(Register-TransferLanguage):

IR=Memory[PC];

PC=PC+4;Step1:InstructionFetch&PCIncrement(IF)Readregistersrsandrtincaseweneedthem.Computethebranchaddressincasetheinstructionisabranch.RTL:

A=Reg[IR[25-21]];

B=Reg[IR[20-16]];

ALUOut=PC+(sign-extend(IR[15-0])<<2);

Step2:InstructionDecodeandRegisterFetch(ID)ALUperformsoneoffourfunctionsdependingoninstructiontypememoryreference:

ALUOut=A+sign-extend(IR[15-0]);R-type:

ALUOut=AopB;branch(instructioncompletes):

if(A==B)PC=ALUOut;jump(instructioncompletes):

PC=PC[31-28]||(IR(25-0)<<2)

Step3:Execution,AddressComputationorBranchCompletion(EX)Againdependingoninstructiontype:Loadsandstoresaccessmemoryload

MDR=Memory[ALUOut];store(instructioncompletes)

Memory[ALUOut]=B;

R-type(instructionscompletes)

Reg[IR[15-11]]=ALUOut;

Step4:MemoryaccessorR-typeInstructionCompletion(MEM)Againdependingoninstructiontype:Loadwritesback(instructioncompletes)

Reg[IR[20-16]]=MDR;Important:Thereisnoreasonfromadatapath(orcontrol)pointofviewthatStep5cannotbeeliminatedbyperformingforloadsinStep4.

Reg[IR[20-16]]=Memory[ALUOut];

ThiswouldeliminatetheMDRaswell.Thereasonthisisnotdoneisthat,tokeepstepsbalancedinlength,thedesignrestrictionistoalloweachsteptocontainatmostoneALUoperation,oroneregisteraccess,oronememoryaccess.

Step5:MemoryReadCompletion(WB)SummaryofInstructionExecutionMulticycleExecutionStep(1):

InstructionFetchIR=Memory[PC];PC=PC+4;4PC+4MulticycleExecutionStep(2):

InstructionDecode&RegisterFetchA=Reg[IR[25-21]]; (A=Reg[rs])B=Reg[IR[20-15]]; (B=Reg[rt])ALUOut=(PC+sign-extend(IR[15-0])<<2)BranchTargetAddressReg[rs]Reg[rt]PC+4MulticycleExecutionStep(3):

MemoryReferenceInstructionsALUOut=A+sign-extend(IR[15-0]);Mem.AddressReg[rs]Reg[rt]PC+4MulticycleExecutionStep(3):

ALUInstruction(R-Type)ALUOut=AopBR-TypeResultReg[rs]Reg[rt]PC+4MulticycleExecutionStep(3):

BranchInstructionsif(A==B)PC=ALUOut;BranchTargetAddressReg[rs]Reg[rt]BranchTargetAddressMulticycleExecutionStep(3):

JumpInstructionPC=PC[31-28]concat(IR[25-0]<<2)JumpAddressReg[rs]Reg[rt]BranchTargetAddressMulticycleExecutionStep(4):

MemoryAccess-Read(lw)MDR=Memory[ALUOut];Mem.DataPC+4Reg[rs]Reg[rt]Mem.AddressMulticycleExecutionStep(4):

MemoryAccess-Write(sw)Memory[ALUOut]=B;PC+4Reg[rs]Reg[rt]MulticycleExecutionStep(4):

ALUInstruction(R-Type)Reg[IR[15:11]]=ALUOUTR-TypeResultReg[rs]Reg[rt]PC+4MulticycleExecutionStep(5):

MemoryReadCompletion(lw)Reg[IR[20-16]]=MDR;PC+4Reg[rs]Reg[rt]Mem.DataMem.AddressMulticycleDatapathwithControlI…withcontrollinesandtheALUcontrolblockadded–notallcontrollinesareshownMulticycleDatapathwithControlIICompletemulticycleMIPSdatapath(withbranchandjumpcapability)NewmultiplexorNewgatesForthejumpaddressMulticycleControlStep(1):

FetchIR=Memory[PC];PC=PC+4;101010X0X00101MulticycleControlStep(2):

InstructionDecode&RegisterFetchA=Reg[IR[25-21]]; (A=Reg[rs])B=Reg[IR[20-15]]; (B=Reg[rt])ALUOut=(PC+sign-extend(IR[15-0])<<2);00X00X30XX01000XMulticycleControlStep(3):

MemoryReferenceInstructionsALUOut=A+sign-extend(IR[15-0]);X200X01X0100MulticycleControlStep(3):

ALUInstruction(R-Type)ALUOut=AopB;0XX000X01X???01ifZero=1MulticycleControlStep(3):

BranchInstructionsif(A==B)PC=ALUOut;0XX00X0110110MulticycleExecutionStep(3):

JumpInstructionPC=PC[21-28]concat(IR[25-0]<<2);0XXX01X0X20MulticycleControlStep(4):

MemoryAccess-Read(lw)MDR=Memory[ALUOut];0XXX1010XX0MulticycleExecutionSteps(4)

MemoryAccess-Write(sw)Memory[ALUOut]=B;0XXX0011XX0100X0X0XX1155RD1RD2RN1RN2WNWDRegWriteRegistersOperationALU3EXTND1632ZeroRDWDMemReadMemoryADDRMemWrite5InstructionI32ALUSrcB<<2PC4RegDst5IRMDRMUX0123MUX01MUX01ABALUOUT012MUX<<2CONCAT2832MUX01ALUSrcAjmpaddrI[25:0]rdMUX01rtrsimmediatePCSourceMemtoRegIorDPCWr*IRWriteMulticycleControlStep(4):

ALUInstruction(R-Type)Reg[IR[15:11]]=ALUOut;(Reg[Rd]=ALUOut)MulticycleExecutionSteps(5)

MemoryReadCompletion(lw)Reg[IR[20-16]]=MDR;100X00X0XX055RD1RD2RN1RN2WNWDRegWriteRegistersOperationALU3EXTND1632ZeroRDWDMemReadM