02集成电路工艺和版图设计(参考).ppt

1、2020/6/19,JianFang,1,集成电路工艺和版图设计概述JianFangICDesignCenter,UESTC,2020/6/19,JianFang,2,微电子制造工艺,2020/6/19,JianFang,3,IC常用术语,园片：硅片芯片(Chip,Die)：6、8：硅（园）片直径：125.4mm6150mm;8200mm;12300mm;亚微米1m的设计规范深亚微米=0.5m的设计规范0.5m、0.35m设计规范（最小特征尺寸）布线层数：金属（掺杂多晶硅）连线的层数。集成度：每个芯片上集成的晶体管数,2020/6/19,JianFang,4,IC工艺常用术语,净化级别：Cla

2、ss1,Class10,Class10,000每立方米空气中含灰尘的个数去离子水氧化扩散注入光刻.,2020/6/19,JianFang,5,生产工厂简介,PSI,2020/6/19,JianFang,6,FabTwowascompletedJanuary2,1996andisaStateoftheArtfacility.This2,200squarefootfacilitywasconstructedusingallthelatestmaterialsandtechnologies.Inthissetofcleanroomswechangetheair390timesperhour,ifyo

3、udothemathwithULPAfiltrationthisisaClassOnefacility.WehavehadittestedanditdoesmeetClassOneparameters(withoutanypeopleworkinginit).Sincewearenotmakingmicroprocessorshereandwedontwanttowearspacesuits,werunitasaclass10fab.EventhoughitconsistentlyrunswellbelowClassTen.,2020/6/19,JianFang,7,HereintheFabT

4、woPhotolithographyareaweseeoneofour200mm.35micronI-LineSteppers.thissteppercanimageandalignboth6&8inchwafers.,2020/6/19,JianFang,8,AnotherviewofoneoftheFabTwoPhotolithographyareas.,2020/6/19,JianFang,9,Hereweseeatechnicianloading300mmwafersintotheSemiTool.Thewafersareina13waferTefloncassetteco-desig

5、nedbyProcessSpecialtiesandSemiToolin1995.Againthesearetheworldsfirst300mmwetprocesscassettes(thatcanbespinrinsedried).,2020/6/19,JianFang,10,AswelookinthiswindowweseetheWorldsFirsttrue300mmproductionfurnace.Ourdevelopmentanddesignofthistoolbeganin1992,itwasinstalledinDecemberof1995andbecamefullyoper

6、ationalinJanuaryof1996.,2020/6/19,JianFang,11,Herewecanseetheloadingof300mmwafersontothePaddle.,2020/6/19,JianFang,12,ProcessSpecialtieshasdevelopedtheworldsfirstproduction300mmNitridesystem!Webeganprocessing300mmLPCVDSiliconNitrideinMayof1997.,2020/6/19,JianFang,13,2,500additionalsquarefeetofStateo

7、ftheArtClassOneCleanroomiscurrentlyprocessingwafers!Withincreased300mm&200mmprocessingcapabilitiesincludingmorePVDMetalization,300mmWetprocessing/Cleaningcapabilitiesandfullwafer300mm.35umPhotolithography,allinaClassOneenviroment.,2020/6/19,JianFang,14,CurrentlyourPS300AandPS300Bdiffusiontoolsarecap

8、ableofrunningboth200mm&300mmwafers.Wecanevenprocessthetwosizesinthesamefurnaceloadwithoutsufferinganyuniformityproblems!(ThermalOxideOnly),2020/6/19,JianFang,15,AccuracyinmetrologyisneveranissueatProcessSpecialties.Weusethemostadvancedroboticlaserellipsometersandothercalibratedtoolsforprecisionthinf

9、ilm,resistivity,CDandstepheightmeasurement.IncludingournewNanometrics8300fullwafer300mmthinfilmmeasurementandmappingtool.WealsouseoutsidelaboratoriesandourexcellentworkingrelationshipswithourMetrologytoolcustomers,foradditionalcorrelationandcalibration.,2020/6/19,JianFang,16,OneoftwoSEMLabslocatedin

10、ourfacility.InthisoneweareusingafieldemissiontoolforeverythingfromlookingatphotoresistprofilesandmeasuringCDstodoublecheckingmetaldepositionthicknesses.Atthehelm,anotheroneofourprocessengineersyoumayhavespokenwithMarkHinkle.,2020/6/19,JianFang,17,HerewearelookingattheIncomingmaterialdispositionracks

11、,2020/6/19,JianFang,18,AboveyouarelookingatacoupleofviewsofthefacilitiesonthewestsideofFabOne.Hereyoucanseeoneofour18.5Meg/OhmDIwatersystemsandoneoffour10,000CFMairsystemsfeedingthisfab(leftpicture),aswellasoneofourwasteairscrubberunits(rightpicture).Bothareinsidethebuildingforeasiermaintenance,long

12、erlifeandbettercontrol.,2020/6/19,JianFang,19,集成电路（IntegratedCircuit,IC）：半导体IC，膜IC，混合IC半导体IC：指用半导体工艺把电路中的有源器件、无源元件及互联布线等以相互不可分离的状态制作在半导体上，最后封装在一个管壳内，构成一个完整的、具有特定功能的电路。,半导体IC,双极IC,MOSIC,BiCMOS,PMOSIC,CMOSIC,NMOSIC,2020/6/19,JianFang,20,MOSIC及工艺,MOSFETMetalOxideSemiconductorFieldEffectTransistor.金属氧化物

13、半导体场效应晶体管,Si,金属,氧化物（绝缘层、SiO2）,半导体,MOS(MIS)结构,2020/6/19,JianFang,21,栅氧化层厚度：50埃1000埃（5nm100nm）VT阈值电压电压控制,N沟MOS（NMOS）,P型衬底，受主杂质；栅上加正电压，表面吸引电子，反型，电子通道；漏加正电压，电子从源区经N沟道到达漏区，器件开通。,2020/6/19,JianFang,22,N衬底,p+,p+,漏,源,栅,栅氧化层,场氧化层,沟道,P沟MOS（PMOS）,VT,VGS,ID,+,-,VDS0,N型衬底，施主杂质，电子导电；栅上加负电压，表面吸引空穴，反型，空穴通道；漏加负电压，空穴

14、从源区经P沟道到达漏区，器件开通。,2020/6/19,JianFang,23,CMOS,CMOS：ComplementarySymmetryMetalOxideSemiconductor互补对称金属氧化物半导体特点：低功耗,VSS,VDD,Vo,Vi,CMOS倒相器,PMOS,NMOS,I/O,I/O,VDD,VSS,C,C,CMOS传输门,2020/6/19,JianFang,24,N-Si,P+,P+,n+,n+,P-阱,D,D,Vo,VG,VSS,S,S,VDD,CMOS倒相器截面图,CMOS倒相器版图,2020/6/19,JianFang,25,ANMOSExample,2020/6

15、/19,JianFang,26,pwell,PwellActivePolyN+implantP+implantOmicontactMetal,2020/6/19,JianFang,27,NtypeSi,SiO2,光刻胶,MASKPwell,2020/6/19,JianFang,28,NtypeSi,SiO2,光刻胶,光刻胶,MASKPwell,2020/6/19,JianFang,29,NtypeSi,SiO2,光刻胶,光刻胶,SiO2,2020/6/19,JianFang,30,NtypeSi,SiO2,SiO2,Pwell,2020/6/19,JianFang,31,pwell,Pwell

16、ActivePolyN+implantP+implantOmicontactMetal,2020/6/19,JianFang,32,NtypeSi,SiO2,Pwell,SiO2,光刻胶,MASKactive,MASKActive,Si3N4,2020/6/19,JianFang,33,NtypeSi,SiO2,Pwell,SiO2,光刻胶,光刻胶,MASKactive,MASKActive,Si3N4,2020/6/19,JianFang,34,NtypeSi,SiO2,Pwell,SiO2,光刻胶,光刻胶,Si3N4,2020/6/19,JianFang,35,NtypeSi,SiO2,P

17、well,SiO2,场氧,场氧,场氧,Pwell,Si3N4,2020/6/19,JianFang,36,NtypeSi,SiO2,Pwell,场氧,场氧,场氧,Pwell,2020/6/19,JianFang,37,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2020/6/19,JianFang,38,active,pwell,PwellActivePolyN+implantP+implantOmicontactMetal,2020/6/19,JianFang,39,NtypeSi,SiO2,Pwell,SiO2,MASKpoly,场氧,场氧,场氧

18、,Pwell,poly,光刻胶,2020/6/19,JianFang,40,NtypeSi,SiO2,Pwell,SiO2,MASKpoly,场氧,场氧,场氧,Pwell,光刻胶,poly,2020/6/19,JianFang,41,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2020/6/19,JianFang,42,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2020/6/19,JianFang,43,active,pwell,poly,PwellActivePolyN+implantP+implant

19、OmicontactMetal,2020/6/19,JianFang,44,NtypeSi,SiO2,Pwell,SiO2,MASKN+,场氧,场氧,场氧,Pwell,poly,光刻胶,2020/6/19,JianFang,45,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,光刻胶,poly,N+implant,2020/6/19,JianFang,46,active,pwell,poly,P+implant,PwellActivePolyN+implantP+implantOmicontactMetal,2020/6/19,JianFang,47,NtypeS

20、i,SiO2,Pwell,SiO2,MASKN+,场氧,场氧,场氧,Pwell,poly,光刻胶,光,2020/6/19,JianFang,48,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,光刻胶,P+implant,2020/6/19,JianFang,49,NtypeSi,SiO2,Pwell,SiO2,场氧,场氧,场氧,Pwell,poly,2020/6/19,JianFang,50,active,pwell,poly,P+implant,N+implant,PwellActivePolyN+implantP+implantOmicontact

21、Metal,2020/6/19,JianFang,51,NtypeSi,SiO2,Pwell,SiO2,MASKOmicontact,场氧,场氧,场氧,Pwell,poly,2020/6/19,JianFang,52,active,pwell,poly,N+implant,omicontact,PwellActivePolyN+implantP+implantOmicontactMetal,2020/6/19,JianFang,53,NtypeSi,SiO2,Pwell,SiO2,MASKmetal,场氧,场氧,场氧,Pwell,poly,metal,metal,metal,2020/6/19

22、,JianFang,54,2020/6/19,JianFang,55,双极型IC及工艺,N,P,N,基极,集电极,发射极,P,N,P,基极,集电极,发射极,C,B,E,IB,IC,IE,C,B,E,IB,IC,IE,NPN晶体管,PNP晶体管,2020/6/19,JianFang,56,VCE,iC,iB,VCE(sat),iR,双极型晶体管输出特性,放大区,饱和区,电流放大能力；电流驱动；,2020/6/19,JianFang,57,基极,发射极,2020/6/19,JianFang,58,BiCMOS:双极(Bipolar)与CMOS相容技术。BiCMOS可以将双极器件与CMOS器件制作在

23、同一芯片上，使之具有双极电路的高速度、高驱动能力、高模拟精度，又具有CMOS电路的低功耗、高集成度等特性。BiCMOS工艺较之CMOS工艺和双极工艺都复杂，制作周期长，产品成品率比CMOS低，成本比CMOS高。高性能双极工艺与CMOS的VLSI工艺80的工艺是相同的，在CMOS生产线上，只要改动或增添一部分工序，增添一部分设备，就可以制作BiCMOS芯片。,BiCMOS,2020/6/19,JianFang,59,版图设计（layout）及相关技术,2020/6/19,JianFang,60,Celldevelopment(Analog/digital)Analogdesign,Schemat

24、icentry(transistorsymbols)Analogsimulation(SPICEmodels)Layout(layerdefinitions)DesignRuleChecking,DRC(designrules)Extraction(extractionrulesandparameters)ElectricalRuleChecking,ERC(ERCrules)LayoutVersusSchematic,LVS(LVSrules),2020/6/19,JianFang,61,LayoutDrawinggeometricalshapes:Defineslayouthierarch

25、yDefineslayermasksRequiresdetailedknowledgeaboutCMOStechnologyRequiresdetailedknowledgeaboutdesignrules(hundredsofrules)RequiresdetailedknowledgeaboutcircuitdesignSlowandtediousOptimumperformancecanbeobtained,2020/6/19,JianFang,62,图形层的定义,N+implant,metal,pwell,active,Poly,定义若干图层,每层对应一张掩膜版,pwell,activ

26、e,poly,N+implant,P+implant,omicontact,metal,2020/6/19,JianFang,63,LibA,LibB,LibC,Cell1,Cell2,Cell3,Tech,inst1,inst2,Inst3,版图库的组织,一个库对应一个特定的工艺针对该工艺的设计规则,和环境设定放在Tech文件中.一个库可以包含若干不同层次的Cell.,2020/6/19,JianFang,64,版图数据交换文件,GDSII格式CIF格式EDIF格式,基本图形,基本操作,2020/6/19,JianFang,65,DRCDesignRuleCheckChecksgeometr

27、icalshapes:width,length,spacing,overlap,etc.,1.单层规则该规则包括各层的最小宽度a及同层间距b,2020/6/19,JianFang,66,CMOS电路规则,2.层间规则（包括各层间的间距、包围、迭搭的大小）,2020/6/19,JianFang,67,说明标号尺寸（um）有源区包围欧姆孔a4金属（铝）包围欧姆孔b3多晶硅包围欧姆孔c4n+、p+注入区包围有源区d5n+、p+保护环有源区e10n+、p+保护环宽度f5nmos、pmos多晶硅栅宽度g6多晶硅栅伸出有源区h12多晶硅栅与n+、p+保护环迭搭i2多晶硅栅铝布线j1p阱包围p+保护环k2.

28、,2020/6/19,JianFang,68,DRC文件例子(片断),(drcmetal(width1.00)(drcmetal(sep0.80),(drcmetalomicont(enc0.30)(drcpolyomicont(enc0.40),2020/6/19,JianFang,69,EXTRACT,用图层间的相对关系判定器件及相互连接关系.例如:Poly跨过Active,即同时出现Poly和Active表明有一个MOS器件.,Extractselectricalcircuit:transistors,connections,capacitance,resistance,2020/6/1

29、9,JianFang,70,EXTRACT文件例子(片断),(extractDevicengate(polyG)(nsdSD)(pwell1B)nmos4symbolanalogLib)(extractDevicepgate(polyG)(psdSD)(subB)pmos4symbolanalogLib)pgateWidth=measureParameter(length(pgatecoincidentpoly)0.5)pgateLength=measureParameter(length(pgateinsidepoly)0.5)saveParameter(pgateWidthW)savePa

30、rameter(pgateLengthL)ngateWidth=measureParameter(length(ngatecoincidentpoly)0.5)ngateLength=measureParameter(length(ngateinsidepoly)0.5)saveParameter(ngateWidthW)saveParameter(ngateLengthL),2020/6/19,JianFang,71,LVS,Layoutversusschematictransistors:parallelorserialCompareselectricalcircuits:(schemat

31、icandextractedlayout),2020/6/19,JianFang,72,ERCElectricalrulecheckCheckselectricalcircuit:unconnectedinputsshortedoutputscorrectpowerandgroundconnection,2020/6/19,JianFang,73,Digitaldesign,Behavioralsimulation.Simulation/timingverificationwithestimatedback-annotationPlaceandroute(placeandrouterules)

32、DesignRuleCheck,DRC(DRCrules)Loadingextraction(rulesandparameters)Simulation/timingverificationwithrealback-annotationDesignexport.,2020/6/19,JianFang,74,PlaceandRoute,GeneratesfinalchipfromgatelevelnetlistGoals:MinimumchipsizeMaximumchipspeed.Placement:PlacingallgatestominimizedistancebetweenconnectedgatesFloorplanningtoolusingdesignhierarchySpecializeda