Cheela1 0 硬體線路說明

1、Cheela 1.0 硬體線路說明 2006/04/17 RDEE3 Erison Lu 製作發行 Tony Fang 指導,Basic concept Block Diagram Power up timing Block Power up flowchart Circuits Exploded Block VGA portion,Agenda,Basic concept,What is the Bus?,A data transmission channel between ICs . Two types Bus Parallel and serial Bus How to debug B

2、us: 每一種 Bus 都有自己的 protocol，傳輸資料時無法以示波器知道 Bus 現在在做什麼(一般以 LA 為工具). 系統設計時就確保 Bus 是健全的, 所以. 先找出那個 Bus 出問題. 若整個 Bus 不動,先查 CLK, power (過 bead)及控制訊號. 目視相關線路零件有無空焊,短路或錯料. 以示波器直接掃瞄 Bus 有無短路,斷路. 照 X ray.,Parallel Bus,D0 . . D64 A3 . . A16 ADS# DRDY# . . TRDY#,D0 . . D64 A3 . . A16 ADS# DRDY# . . TRDY#,Data Bu

3、s,Address Bus,Control Bus,Clocks,Parallel Bus 有 FSB, PCI, IDE, DDR, FDD, Parallel port,Serial Bus,Data CLK,Data CLK,Data/Address/Control Bus,Serial Bus 有 DMI, PCIE, SATA, AC97, USB, IR,IC active sequence,Power,Clocks,Power good,Reset,Some ICs complete Power good and Reset together ex. ICH,What is +V

4、?A, +V?, +V?S,電源插入時,系統開機後,系統進入待命,系統關機或進入休眠,+V?A,+V?A, +V?, +V?S,+V?A, +V?,+V?A,Block Diagram,Cheela 1.0 Block Diagram,Power up timing Block,Power up timing Block,KBC,ICH,Power IC,Charger,Clock-G,NB,CPU,Reset IC / DC +V3A/+V5A,Adapter,Battery,+VBAT,+V3A/+V5A,1,2,3,Power button,4,RSMRST#,5,SLP_S5/S4/S

5、3,6,7,IMVP_CKEN,8,Clocks out,Power up timing Block Cont.,KBC,ICH,Power IC,Charger,Clock-G,NB,CPU,Reset IC / DC +V3A/+V5A,PWROK,9,PLT_RST#,11,H_CPURST#,12,H_ADS#,13,H_PWRGD,10,Cheela 1.0 power up timing,Cheela 1.0 power up timing cont.,Cheela 1.0 Power up timing cont.,Power up flowchart,Power Up Flow

6、chart First Step Power In,Charger Circuits U35 (sheet5) Ti_BQ24721,Adapter In 19V OR Battery In,+V5LA source U26 (sheet7) Ti_TPS51020DBT,Reset IC U38 (sheet6) GMT_G680LT1,+VBAT,+VBAT,+V5LA,+V5AUXON,DC/DC (+V3A/+V5A) U26 (sheet7) Ti_TPS51020DBT,+V_RTC source D501 (sheet 40) BAT54C,+V5AUXON,+VBAT,+V3A

7、,+V5A,+V_RTC,KBC active U509 (sheet57) KBC1122,BIOS CN24 (sheet57) SST_39VF040,Access BIOS,Power Up Flowchart 2th Step Push power button,This page shows power sequence between power button to all system powers up,KBC1122 U509 (sheet57),ICH7 U39(sheet4044),U36 (sheet9) Ti_TPS51124RGER,U505 (sheet8) T

8、i_TPS51124RGER,Q4 (sheet11) FDS8426A,+V3A,32.768KHz,PWR_SWIN#_3,32.768KHz,+V_RTC,LOW_BAT#,Q28/Q29 (Sheet12) Q39/Q516,U505 (sheet8) Ti_TPS51124RGER,+VGAVCC,+V1.5S,+V1.5_PWRGD,+V1.8,U17(sheet11) GMT_G966,U18(sheet11) GMT_G2997F6U,RSMRST#,+V1.8S,+VGAVCC_PWRGD,+V5S,+V3S,+V1.2S,+V0.9S,M_VFER,+VGAVCC_PWRG

9、D,SLP_S3#_3R,SLP_S4#_3R,SLP_S3#_3R,SLP_S4#_3R,U16 (sheet6) GMT_G966,+V2.5S,+V5S,+V1.5S,Power Up Flowchart 3th Step CPU power up and Reset timing,U511 (sheet11) NC7WZ17,U22(sheet10) ADI_ADP3207,CN13 (sheet1415) CPU,U36 (sheet9) Ti_TPS51124RGER,U39 (sheet41) ICH7M-DH,+V1.5_PWRGD,SLP_S3#_3R,VR_PWRGD_CK

10、410,+V5AUXON,VR_PWRGD_CK410,U21 (sheet10) NC7WZ17,+VCCP,IMVP_CKEN#,U23 (sheet19) Calistoga,U509 (sheet57) KBC1122,PWR_GOOD_3,PM_PWROK,IMVP_CKEN#,MCH_GOOD,Clocks,+VCC_CORE,SLP_S3#_3R,SB_3S_VRMPWRGD,PLT_RST#,H_CPURST#,U37 (sheet13) ICS9LPR316,H_ADS#,H_PWRGD,Circuits Exploded Block,Reset IC,Page 6,ther

11、mal IC 過熱時會透過KBC 拉 low 關閉整個系統電源,開啟 +V3A/+V5A 的第一個訊號,+VBAT (lo)= 7.59V = 1.245 X( R1+R2+R3) / (R2+R3) +VBAT (hi)= 8.27V = 1.245 X (R1+R2+R3) / R3,+V5AUXON will declare DC/DC circuits to output +V3A/+V5A,(R1),(R2),(R3),Another control logic for +V5AUXON,This pin connect to HotkeyBoards power button.,E

12、SD protection,Q514-G inactive condition: Push power button. Ac adapter in KBC tie BATT_PWRKEEP,也就是說DC mode要等user按power Bottom才會將+V5A,+V3A打開 AC mode EC會自動將 +V5A, +V3A always 的電打開,Page 6,DC/DC +V3A, +V5A, +V5LA,Page 7,+V5AUXON will turn on +V3A/+V5A,+V5LA is transferred by U24s internal LDO, so it com

13、es once +VBAT up.,EC active,KBC 第一次 收到 PWR_SWIN#_3 low 時, 會把 RSMRST# 拉 high to reset ICH,Page 57,這是Power Switch 的訊號,RSMRST# is for KBC to reset ICH,Make sure 32.768KHz is oscillating.,EC_PWRSW# is for KBC to power on ICH, In normal it will be high.,南橋要開電前的必要條件,RTC have to be oscillating(32.768KHz).

14、RTCRST# have to be high. RSMRST# have to be inactive (high). PWRBTN# have a trigger. LOW_BAT#_3 have to be inactive (high). If true, then ICH will issue SLP_S3#_3R / SLP_S4#_3R.,Page 41,Page 40,南橋會送出S3#,S5#的訊號去開啟 系統 +V? +V?S 的電源,Page 41,SLP_S3#_3R turn on +V?S powers,SLP_S4#_3R turn on +V? powers,南橋

15、會送出 SLP_S3/SLP_S4 去開啟系統所有需要的電源,Page11,電源概分兩種 : PWM & LDO. 但開電的必要條件都一樣 source power, enable pin,以下兩種線路都是 LDO type,Source power,Enable Pin,Page8,南橋會送出 SLP_S3/SLP_S4 去開啟系統所有需要的電源,以下為 PWM type,Enable Pin,+VBAT,Source power,Power_Good訊號的產生與目的,Page 11,When All +V?S/+V? powers are ready, PWR_GOOD_3 will ti

16、e to high to turn on CPU powers (+VCCP and +VCC_CORE).,確認CPU外的電源都已起穩定, 並準備去開 CPU powers.,開啟+VCCP電源和 MCH_GOOD的產生,Page 9,When +VCCP is ready, this DC circuits will issue MCH_GOOD to turn on +VCC_CORE.,PWR_GOOD_3 turn on +VCCP,開啟+VCC_CORE電源和 VR_PWRGD_CK410 / IMVP_CKEN# 的產生,Page 10,MCH_GOOD enable IMVP

17、to generate +VCC_CORE,When +VCC_CORE power is ready, VR_PWRGD_CK410 will go high to inform system that CPU powers are ready.,When +VCC_CORE is ready, IMVP_CKEN# will go high to enable clock-G,CLOCKs 的產生,Page 13,Turn on all clocks by IMVP_CKEN#,VREF is to adjust driver output strength,PCI_SRC_STOP# a

18、nd CPU_STOP# must be at high otherwise some clocks will be turned off.,CLOCKs 的產生 cont.,Page 13,CLKREQx can separately control one pair SRC on/off.,Clocks distribution,For Reference Only,Chipsets power good 產生,Page 10,當 CPU power 穩定時, 用 VR_PWRGD_ck410 經 delay線路產生 SB_3S_VRMPWRGD通知南橋及KBC cpu 電源已穩定,為確保

19、 clocks 已穩定送出, 所以再經一次 delay 送出 PM_PWROK 給南北橋,南橋Power Good的來源,南橋收到這兩個power good 訊號後,會reset內部的邏輯線路,並發 H_PWRGD 告之CPU 電源控制部分已備妥. 接著發 PLT_RST# reset 北橋, 然後起動DMI 與 北橋溝通.,Page 41,RESET北橋,南橋會送PLT_RST#來Reset北橋,Page 19,RESET CPU,Page 15,First, ICH will tie H_PWRGD to high,Then NB will tie CPURST# to reset CPU.,Page 14,FSB BUS 的第一個訊號,ADS# 是 RESET CPU後的第一個系統訊號去和北橋溝通,Page 14,DMI 的第一個訊號,這是北橋和南橋間的溝通訊號,Page19,ICH 與 KBC 間的 Bus - LPC LPC 的第一個訊號,量測FRAME#看 LPC是否有動作,Page 40,系統讀 FLASH ROM 的第一個訊號,量測FLASH看系統是否有解到FLASH ROM的第一個位址,Page 57,VGA portion,NVIDIA G73M GPU power sequence,黑屏當在 4E,