计算机设计与实践——32位先行进位加法器ppt课件

1、.,32位先行进位加法器,Verilog HDL语言,.,32位超前进位加法器的进位是并行同时产生的，能够极大的减少加法器由进位引起的延时。增加了逻辑器件，但有效的减少的延迟。进位是由cla部件超前算出，本位是由不含进位的加法器算出。,.,Verilog HDL代码如下： module alu_32(c2,f32,x32,y32,ciii);/32位加法器先行进位加法器 input 32:1x32; input 32:1y32; input ciii; output 32:1f32; output c2; wire c1; wire 2:1p; wire 2:1g; alu_16 alu_16

2、_1(g1,p1,f3216:1,x3216:1,y3216:1,ciii); alu_16 alu_16_2(g2,p2,f3232:17,x3232:17,y3232:17,c1); assign c1=g1|p1 endmodule,.,module alu_16(gmm,pmm,f16,x16,y16,cii);/16位加法器先行进位加法器 input 16:1x16; input 16:1y16; input cii; output 16:1f16; output gmm,pmm; wire 4:1c; wire 4:1p; wire 4:1g; jiafaqi_4 alu_4_1(

3、g1,p1,f164:1,x164:1,y164:1,cii); jiafaqi_4 alu_4_2(g2,p2,f168:5,x168:5,y168:5,c1); jiafaqi_4 alu_4_3(g3,p3,f1612:9,x1612:9,y1612:9,c2); jiafaqi_4 alu_4_4(g4,p4,f1616:13,x1616:13,y1616:13,c3); cla_4 cl_4_1(c,p,g,cii); assign pmm=p4 endmodule,.,module jiafaqi_4(gm,pm,f,x,y,c0); /四位超前进位加法器 input 4:1x;

4、/四位x值 input 4:1y; /四位y值 output 4:1f; /四位加和f output gm,pm; input c0; /上一的级进位 wire 3:1c; /超前进位 wire 4:1p; wire 4:1g; assign p=x|y; assign g=x endmodule,.,module jiafaqi_1(x,y,c0,f); /一位加法器模块 input x; input y; input c0; output f; assign f=(xy)c0; endmodule module cla_4(c,p,g,c0);/4位CLA部件 input 4:1p; in

5、put 4:1g; input c0; output 4:1c; assign c1=g1|p1 endmodule,.,测试代码： module test; reg 32:1 x32; reg 32:1 y32; reg ciii; wire c2; wire 32:1 f32; alu_32 uut ( .c2(c2), .f32(f32), .x32(x32), .y32(y32), .ciii(ciii) );,.,initial begin x32 = 0; y32 = 0; ciii = 0; #100; x32 = 32haaaaaaaa; y32 = 32h55555555; ciii = 0; #100; x32 = 32haaaaaaaa; y32 = 32h55555555; ciii = 1; #100; x32 = 32h00000011; y32 = 32h0000