北科自动化数电

1、CHAPTER 6 Functions of Combinational Logic,6-1 Basic Adders 6-2 Parallel Binary Adders 并行二进制加法器 6-3 Comparators 比较器 6-4 Decoders 译码器 6-5 Encoders 编码器 6-6 Code Converters代码转换器 6-7 Multiplexers (Data Selectors) 数据选择器/多路复用（MUX） 6-8 Demultiplexers多路分用器/解双工器（DEMUX） 6-9 Parity Generator/Checker 奇偶校验器,Intr

2、oduction to Several MSI Combinational Circuits介绍几种常用的中规模组件,In this chapter you should know:,The internal functional principle of every MSI chips (in brief) Those MSI chips are combinational circuit (that means they are composed of logic gates); you should learn how to use them Focus on these two blo

3、cks named decoder and data selector which can be used to produce some given logic function,6-1 Basic Adders (implementing 1-bit addition) 基本加法器,6-1-1 Half-Adder 半加器 6-1-2 Full-Adder 全加器 6-1-3 Full adder from two half-adder circuits,General rules of binary addition：,a. Produce a carry bit whenever we

4、 have 2,b. LSB addition:without considering the carry bit。,c. When processing the other bits,we should accept three numbers(two input bits and a carry bit),d. Any two bits will produce a sum bit and a output carry when be added.,Half-adder,Full-adder,6-1-1 Half-Adder(半加器),How could we implement this

5、 function using logic circuit?,A half-adder is a combinational logic circuit that add together two one-bit values and produces a sum and a carry output. The half part of the name comes from the lack of a carry input.,A full-adder is a combinational logic circuit that adds two one-bit values plus a c

6、arry bit and produces a sum and a carry output. The full part of the name comes from the carry input bit.,6-1-2 Full-Adder 全加器,Truth table,Sketch the internal logic circuit of full-adder according to the boolean expression.,6-1-3 Full adder from two half-adder circuits,6-2 Parallel Binary Adders (im

7、plementing more-bit addition) 并行二进制加法器,6-2-1 Two-bit parallel binary adder 6-2-2 Four-bit parallel binary adder,How could a n-bit parallel adder be constructed? A n-bit adder requires n-1 full-adders and one half-adder. How could a full-adder be functioned as a half-adder?,6-2-1 Two-bit parallel bin

8、ary adder,Using two full-adders to implement A2A1+B2B1,the pins of double-full-adder SN74LS183,6-2-2 Four-bit parallel binary adder 四位并行二进制加法器,ripple carry（串行进位） adder showing “worst-case” carry propagation delays.,Cascading Full-Adders 串行全加器,Look-Ahead Carry adder:超前进位加法器：,Carry generation :Cg Carr

9、y propagation :Cp,P191 four full-adders output equation.,4位超前进位加法器74LS283内部结构,Another application of adder:A voting system,6-3 Comparators 数值比较器,A comparators is a combinational logic circuit that compares two binary input values and produces results that specify the relative value of one input with

10、 respect to the other. Outputs of some comparators specify whether A=B, others may specify A=B,AB and Ab3 1 0 0,a3=b3 a2=b2 a1= b1 a0 =b0 0 1 0,a3=b3 a2=b2 a1= b1 a0 b0 1 0 0,a3=b3 a2=b2 a1 b1 1 0 0,a3=b3 a2b2 1 0 0,a3 b3 0 0 1,根据比较规则，可得到四位数值比较器逻辑式：,A=B:,AB:,AB:,Pin diagram and logic symbol for the

11、74HC85 4-bit magnitude comparator.,A=B:,AB:,AB:,例1：七位二进制数比较器。（采用两片85）,必 接 好,(1),(2),高位片,低位片,6-5 Encoders 编码器,Encoders,An encoder is a combinational logic circuit that accepts 2n binary inputs and produces n data encoded output values. An 8-to-3 encoder has eight input lines and three output lines. W

12、hen one of the data inputs is active, the output code that represents that value is generated.,8-line-to-3-line encoder（8线-3线编码器） 2 priority encoder(优先编码器) 3 Decimal-to-BCD encoder（二十进制编码器）,8-line-to-3-line encoder,设八个输入端为I1I8，八种状态，与之对应的输出设为F1、F2、F3，共三位二进制数。,设计编码器的过程与设计一般的组合逻辑电路相同，首先要列出状态表（即真值表），然后写

13、出逻辑表达式并进行化简，最后画出逻辑图。,Truth table (active-low input),Logic diagram,Priority encoder (优先编码器),Logic diagram of 74LS148,选通输入端,选通输出端,扩展端,Function description,Function table of 74LS148,Example: 用两片74LS148接成16线4线优先编码器,二-十进制编码器的作用：将十个状态（对应于十进制的十个代码）编制成BCD码。,十个输入,四位,输入：I0 I9,输出：F4 F1,Decimal-to-BCD encoder,L

14、ogic symbol for a decimal-to-BCD encoder.,Truth table,Active-low input,Pin diagram and logic symbol for the 74HC147 decimal-to-BCD priority encoder (HPRI means highest value input has priority).,Application: A simplified keyboard encoder.,Assignments: (due to next Monday),P232 6、8、12 补充作业题： 用4片74LS1

15、48组成32线5线优先编码器，允许附加必要的门电路。,6-4 Decoders 译码器,6-4-1 Binary decoder（二进制译码器） 6-4-2 BCD-to-decimal decoder （BCD码-十进制译码器） 6-4-3 BCD-to-7-segement decoder （BCD码-七段显示驱动译码器）,6-4-1Binary decoder,二进制译码器的作用：将n种输入的组合译成2n种电路状态。也叫n-2n线译码器。,译码器的输入,一组二进制代码,译码器的输出,一组高低电平信号,Binary inputs Active-low outputs,4-line-to-1

16、6-line decoder,What do you figure out from the above truth table?,n-2n 线译码器，包含了n变量所有的最小项。 加上或门或与非门，可以组成任何形式的输入变量小于n的组合逻辑函数。,若要产生多输出逻辑函数时, 使用译码器+门电路较有利。,例：用2-4线译码器产生一组多输出函数。,接线图,练习题：用74LS138译码器和门电路产生如下多输出逻辑函数。,3-line-to-8-line 74LS138 decoder,译码器的多片扩展,利用译码器的使能控制端可以将多片n-2n线译码器组成（n+1）-2（n+1）线译码器或更大的译码器

17、。,例：用两片74LS138接成4线16线译码器,6-4-2 BCD-to-decimal decoder,二-十 进制编码,显示译码器,显示器件,在数字系统中，常常需要将运算结果用人们习惯的十进制显示出来，这就要用到专门的显示译码器。,显示器件：常用的是七段显示器件。,6-4-3 BCD-to-7-segement decoder,LED:light-emitting diode 发光二极管,LCD:liquid crystal display 液晶显示器,Arrangements of 7-segment LED displays.,a,b,c,d,f,g,a b c d e f g,1

18、1 1 1 1 1 0,0 1 1 0 0 0 0,1 1 0 1 1 0 1,e,七段显示器件的工作原理：,Step 1. The 1s are mapped directly from the above table. Step 2. All of the “dont care” are placed on the map. Step 3. The 1s are grouped as shown P144 figure 4-46 Minimum SOP logic expression for the segment-a .,显示译码器：,74LS49的管脚图,74LS49的功能表（简表）

19、,8421码,译码,显示字型,74LS49与七段显示器件的连接：,74LS49是集电极开路，必须接上拉电阻,关于OC门的介绍：,6-8 Multiplexers (Data Selectors) 多路复用器/数据选择器（MUX）,A MUX is a device that allows digital information from several sources to be routed onto a single line for transmission over that line to a common destination. The basic multiplexer has

20、 several data-input lines and a single output line.,从一组数据中选择一路信号进行传输的电路，称为数据选择器。,6-7-1 4-input multiplexer 6-7-2 Expanded multiplexers 6-7-3 Multiplexer as a logic function generator,控制信号,输入信号,输出信号,数据选择器类似一个多路开关。选择哪一路信号由相应的一组控制信号控制。,6-7-1 4-input multiplexer,4-input multiplexer,Waveform,双4选1数据选择器74LS153,功能表,例：用一片74LS153组成8选1: A2=0:(1)工作； A2=1:(2)工作。,6-7-2 Expanded multiplexers,Pin