股票外汇技术分析英文版ppt (6).ppt

1、Design and System Driver Chapters Spring Meeting April 2005Munich, GermanyDesign TWG (Europe, Asia, and U.S.),Albin, Arledge, Asada, Bernstein, Bertacco, Blaauw, Blanton, Brederlow, Briere, Carballo, Chen, Cohn, Cottrell, Darringer, Edwards, Furui, Gowda, Guardiani, Hiwatashi, Kahng, kashiwagi, Kawa

2、hira, Kozawa, Ishibashi, Kravets, Martin, McMillan, Nassif, Pan, Macd, Nukiyama, Pitchumani, Pixley, Rosenstiel, Read, Rodgers, Sakallah, Smith, Soma, Stok, Vertregt, Wilson, Yamamoto, Yamada, Yeh,2005 Spring Deliverables,10 new table drafts quantify design technology trends Final version targeted b

3、y June DFM preliminary model enables variability roadmap DFM roadmapping tool + interface with other groups Draft SoC cost model provides new type of driver SoC model quantifies productivity and architecture trends,Timeline,Design: Content organization,Promotion of key design challenges Small subset

4、 of them to top-level ORTC,Design process,System design,Logic/circuit Physical D,Design verification,Design Test,DFM (new),Productivity,Power,DFM,Interference,Reliability,General,Selection,Mapping,Design: Content organization (II),Scope Complexity and Crosscutting Challenges Design Technology Challe

5、nges - Overall Challenges (5 challenges + table) - Design Methodology Trends (text) - System-level Design - Logical, Circuit, and Physical Design - AMS and RF-specific DT Trends and Challenges (revised) - Design Verification - Design Test,Detailed Table Status,Targeting 50-60 new rows Leads: Rosenst

6、iel, Soma, Bertacco, Kravets, Nassif/Kahng Next steps Incorporate input until final version Complete coloring,New Table: System-Level Requirements,Source: Wolfgang Rosenstiels Team,New Table: System-Level Solutions,Source: Wolfgang Rosenstiels Team,2021,New Table: Logic/Ckt/Physical Requirements,Sou

7、rce: Victor Kravetss Team,New Table: Logic/Ckt/Physical Requirements,Source: Victor Kravetss Team,New Table: Verification Requirements,Verification requirements,Bugs escape rate: bugs found after first tape out. bugs found after system integration until tape-out Code coverage percent of code coverag

8、e Functional coverage percent of the projects where it is used functional coverage goals for each thousand lines of HDL code correlation of size of functional coverage goal vs. escape rate Tape-out criteria examples: booting linux, total number of simulation cycle run, coverage. Reuse ratio of fresh

9、 verification infrastructure vs. reused percent of reused infrastructure that is acquired from third parties Methodology effort spent in formal verification vs. simulation/emulation (in engineering days) effort spent in formal verification vs. simulation/emulation (in lines of HDL),Source: Valeria B

10、ertaccos Team,New Table: DFT Requirements,Source: Mani SomasTeam,New Table: DFM Requirements,Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong,New Table: DFM Solutions,Source: Carballo/Nassif/Pan/Kahng/Guardiani/Brederlow/Wong,2. SoC Cost Model Update, Inc. SW,Mobile /Consumer SoC,Memory,PE

11、-1,Peripherals,PE-2,PE-n,Main Prc.,Updated productivity table cost,Will preserve consistency,# of Processing Engines,Processing Power Trends,HW Design Productivity Requirements,3. New DFM Section Outline,INTRO DFM CHALLENGES - NEAR TERM (45 NM) MASK COST DATA EXPLOSION LIMITATIONS OF LITHOGRAPHY HAR

12、DWARE RESOLUTION VOLTAGE SUPPLY AND THRESHOLD VARIABILITY BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY HETEROGENEOUS COMPONENTS (AMS, MEMS, ERAM) LEAKAGE AS A LIMITER OF MANUFACTURABILITY VARIABILITY DFM CHALLENGES - LONG TERM (45 NM) -UNCONTROLLABLE CD AND DOPING VARIABILITY -EXTREME DEVICE AND C

13、IRCUIT VARIABILITY RET-awareness IN DESIGN PACKAGE, SYSTEM, AND SW VARIABILITY BEOL PLANARIZATION AND DIMENSIONAL VARIABILITY DESCRIPTION OF VARIABILITY MODEL,DFM Variability Framework,NA,Leff,Weff,W,L,t,tOX,tILD,Vt,Intermediate parameters,Intermediate parameters,“Gate” delay (power),“Wire” delay (power),Performance (delay),Power (energy),Rsheet,(Vdd, T),Other TWGs