数字逻辑设计及应用教学课件：8-2 时序电路的设计 计数器

1、Review of the last class,8.4.3 MSI Counters and Applications4位二进制计数器74x163,74x161异步清零,Connections for the 74X163 to operate in a free-running mode(P715) 74x163工作于自由运行模式时的接线方法,A free running divide-by-16 counter,a free-running 163 can be used as a divide-by-2, -4, -8, or -16 counter, by ignoring any

2、unnecessary high-order output bits.,Other MSI counters,1bit BCD counter 74x160 Synchronous clear 、 74x162 Asynchronous clear,74x160、74x162,the counting sequence is modified to go to state 0 after state 9. In other words, these are modulo-10 counters, sometimes called decade counters. the QD and QC o

3、utputs have one-tenth of the CLK frequency, they do not have a 50% duty cycle, and the QC output.,Other MSI counters,74x169-up/down counter,UP/DN,UP/DN = 1 counts up （升序） UP/DN = 0 counts down（降序）,SDATA, application of the counter,Timing diagram for a modulo-8 binary counter and decoder,showing deco

4、ding glitches.,若在一次状态转移中有2位或多位计数位同时变化， 译码器输出端可能会产生“尖峰脉冲” 功能性冒险,More better way 。,A modulo-8 binary counter and decoder with glitch-free (无尖峰)outputs.,Modulo-m counter,Use SSI device Clocked Synchronous State-Machine Design Use MSI counter using n bit binary counter as a modulo-m counter in two cases

5、： m 2n,Although the 163 is a modulo-16 counter, it can be made to count in a modulus less than 16 by using the CLR_L or LD_L input to shorten the normal counting sequence.,using the 163 as a modulo-11 counter(用4位二进制计数器74x163实现模11计数器),清零法,计数到1010时， 利用同步清零端 强制为0000。, m2n,思考： 如果是74x161 （异步清零） 可以这样连接吗？,

6、 利用1011状态异步清零，会出现“毛刺”,Modulo-m counter,This circuit uses a NAND gate to detect state 10 and force the next state to 0. Notice that only a 2-input gate is used to detect state 10 (binary 1010). Although a 4-input gate would normally be used to detect the condition CNT10 = Q3 Q2 Q1 Q0, the 2-input gat

7、e takes advantage of the fact that no other state in the normal counting sequence of 010 has Q3 = 1 and Q1 = 1. In general, to detect state N in a binary counter that counts from 0 to N, we need to AND only the state bits that are 1 in the binary encoding of N.,using the 163 as a modulo-11 counter,置

8、数法, m2n 情况,计数到1111时， 利用同步预置数端 强制输出为0101,using the 163 as a modulo-11 counter,置数法, m2n 情况,计数到1111时， 利用同步预置数端 强制输出为0101,A 74x163 used as an excess-3 decimal counter 74x163用作余3码计数器,1 1 0 0,A 74x163 used as an excess-3 decimal counter 74x163用作余3码计数器,Q3 has one-tenth of the CLK frequency .the Q3 output h

9、as a 50% duty cycle,Cascading 74x163s(计数器的级联),Modulo m counter（ m 2n）,先进行级联，再整体置零或预置数 例：用74x163构造模193计数器 两片163级联得8位二进制计数器（0255） 采用整体清零法，0192 采用整体预置数法，63255 25619363 若 m 可以分解：m = m1m2 分别实现m1和m2，再级联,6310 = ( 0011 1111 )2,What is the modulo of the circuit below?,QD QC QB QA 0 0 0 0 0 1 1 0 0 1 1 1 1 0

10、0 0 1 1 1 0 1 1 1 1,Modulo 12 counter QD：12分频 占空比50,What is the modulo of the circuit below?,A shift register is an n-bit register with a provision for shifting its stored data byone bit position at each tick of the clock.,8.5 Shift Registers,8.5.1 shift register Structure （,a serial-in, serial-out

11、shift register (串入串出移位寄存器),可以使一个信号延迟 n 个时钟周期之后再输出,A serial-in, parallel-out shift register 串入并出移位寄存器结构,可以用来完成 串并转换 serial-to-parallel conversion,a parallel-in, serial-out shift register. 并入串出移位寄存器结构,多路复用结构,SERIN,parallel-in, parallel-out shift register 并入并出移位寄存器结构,SERIN,8.5.2 MSI Shift Registers(MSI

12、移位寄存器),an MSI 4-bit bidirectional, parallel-in, parallel-out shift register (4位双向移位寄存器74x194),left-in 左移输入,right-in 右移输入,left means “in the direction from QD to QA,” right means “in the direction from QA to QD.”,Function table for the74x194 4-bit universalshift register,保持,Qi* = S1S0Qi + S1S0Qi-1 +

13、S1S0Qi+1 + S1S0INi,The 74x194 4-bit universalshift register,CLK CLR S1 S0,移 位 寄 存 器 的 扩 展,8.5.3 Shift-Register Counters,Serial/parallel conversion is a “data” application, but shift registers have “nondata” applications as well. A shift register can be combined with combinational logic to form a sta

14、te machine whose state diagram is cyclic. Such a circuit is called a shift-register counter. Unlike a binary counter, a shift-register counter does not count in an ascending or descending binary sequence, but it is useful in many “control” applications.,8.5.5 Shift-Register Counters(移位寄存器计数器),D0 = F

15、 ( Q0 , Q1 , , Qn-1 ),一般结构：,1000,8.5.6 Ring Counters (环型计数器),D0 D1 D2 D3, 非自启动的,无效状态,D0 = Qn-1,self-correcting counter,self-correcting counter is designed so that all abnormal states have transitions leading to normal states. Self-correcting counters are desirable for the same reason that we use a minimal-risk approach to state assignment : If something unex