《布局布线流程》PPT课件.ppt

1、深亚微米后端设计流程,许可敬 2009-12-21,Digital Flow Overview,准备工作,工具准备 Soc-encounter Voltagestorm Celtic fire_ice virtuso Dracula or calibre primetime,文件准备 Verilog LEF LIB 时序约束文件 IO文件 DRC，LVS rule 文件,Library Exchange Format (LEF),Timing library,cell (INVX1) cell_footprint : “inv”; area : 36.000000; cell_leakage_

2、power : 6.883686e+01; leakage_power () when : “A”; value : “60.524918”; leakage_power () when : “!A”; value : “68.836860”; pin (A) direction : “input”; pin (Y) direction : “output”; function : “(!A)”; max_capacitance : 0.510000; internal_power () related_pin : “A”; rise_power (“power_outputs_1”) ; f

3、all_power (“power_outputs_1”) “); ,timing () related_pin : ”A“; timing_type : ”combinational“; timing_sense : ”negative_unate“; cell_fall (del_1_7_7) index_1(0.05, 0.1, 0.3, 0.8, 1.3, 1.9, 2.6); index_2(0.0006, 0.03, 0.06, 0.15, 0.27, 0.39, 0.51); values(0.025, 0.088, 0.149, 0.333, 0.578, 0.827, 1.0

4、70, 0.026, 0.096, 0.157, 0.340, 0.586, 0.835, 1.077, 0.015, 0.118, 0.191, 0.373, 0.618, 0.860, 1.104, -0.031, 0.117, 0.221, 0.456, 0.706, 0.946, 1.187, -0.084, 0.092, 0.217, 0.496, 0.790, 1.040, 1.278, -0.153, 0.051, 0.193, 0.515, 0.849, 1.132, 1.389, -0.235, -0.006, 0.155, 0.517, 0.887, 1.207, 1.48

5、7); fall_transition (del_1_7_7) index_1(0.05, 0.1, 0.3, 0.8, 1.3, 1.9, 2.6); index_2(0.0006, 0.03, 0.06, 0.15, 0.27, 0.39, 0.51); values(0.026, 0.118, 0.223, 0.518, 0.920, 1.332, 1.755, 0.035, 0.120, 0.218, 0.518, 0.935, 1.345, 1.756, 0.065, 0.173, 0.251, 0.519, 0.938, 1.321, 1.722, 0.130, 0.291, 0.

6、387, 0.632, 0.951, 1.322, 1.721, 0.181, 0.382, 0.509, 0.784, 1.079, 1.391, 1.742, 0.238, 0.485, 0.626, 0.930, 1.263, 1.566, 1.866, 0.304, 0.595, 0.755, 1.109, 1.464, 1.790, 2.093); ,时序约束文件,create-clock - period EXTCL K- PERIOD - name exclkEXTCL K- PORT set-min-pulse-width expr 0. 4 3 EXTCL K- PERIOD

7、 getclocks exclk set- drive 0 EXTCL K- PORT set-clock- uncertainty EXTCL K- SKEW get-clocks exclk set-clock-latency2source 1 exclk set-max- delay 502from get-ports EXTRST- P set-input- delay2max 22clock exclk get-ports AASPE- P set-output- delay2max 12clock exclk get-ports RPO 3 create-clock2period

8、BUSCL K- PERIOD2name baclk get-ports BACL K- P set-min-pulse-width expr 0. 4 3 BUSCL K- PERIOD getclocks baclk set-propagated-clock baclk set- dont- touch- network get-clocks baclk set-false-path from get-clocks bdclk to get-clocks exclk set- dont- touch- network Top-Core/ cpu-interface1/ reset-int

9、Set_clock_gating_check rise setup 0.1 Set_clock_gating_check rise hold 0.2,IO location file,Version: 2 Offset: 19.4700 Pin: address14 N 0.4200 0.2800 Offset: 39.2700 Pin: address10 S 0.5600 0.2800,soc encounter 一般流程,Design After input,Top-Level Implementation Steps,Run timing analysis. Analyze timin

10、g with the Common Timing Engine (CTE) using zero net loading to determine whether the initial design meets timing requirements. Place I/O, power, and ground pads. If you provide an I/O assignment file, you are not required to specify the exact location of allI/O pads. Place JTAG (boundary scan)cells

11、. Specify and place JTAG cells near the I/O cells. Once placed, they will not be moved in subsequent placement runs. Place the blocks in the design if you have an all-block. You can use the Encounter block placer or manually place blocks. Critical cell placement. we must plase some crital cell manua

12、lly after “JTAG cell placement” this cell like the buffers. Power plan. Define the power rings and stripes.,Top-Level Implementation Steps,Run Amoeba placement. Use the Amoeba placer to place cells in the design. The placer places cells according to module guide and fence constraints. Running placem

13、ent and analyzing the congestion lets you quickly gauge the feasibility of the design in meeting timing and placement density goals. Congestion Analysis Can evaluate the designs congestion ,if its results can be acceptable, we can go to next step, othewise must re-do placement optimization. Reorder

14、scan chains. Refine the initial scan-chain order based on Amoeba placement results. Although changes made at this step are not used after the initial floorplanning, this step is still recommended for reducing wire length for a more accurate analysis of congestion. Refine the initial scan-chain order

15、 based on the most recent Amoeba placement results.,After place and power plan,Top-Level Implementation Steps,Build clock tree Define clock tree constraints, such as insertion delay and skew limits. Synthesize the clock tree. Analyze the clock tree reports to determine if timing constraints have bee

16、n met. At this stage, netlist changes are not passed forward. A clock tree is generated to determine clock and timing issues with the current floorplan. Run in-place optimization (IPO). Run in-place optimization, which adds buffer cells, resizes gates, and fixes design rule violations. Although netl

17、ist changes made at this stage are not kept, in-place optimization is necessary for assessing potential timing issues with the current floorplan.,静态时序分析,静态时序分析技术是一种穷尽分析方法,用以衡量电路性能。它提取整个电路的所有时序路径,通过计算信号沿在路径上的延迟传播,找出违背时序约束的错误,主要是检查建立时间和保持时间是否满足要求,而它们又分别通过对最大路径延迟和最小路径延迟的分析得到。 Setup Timing Arc：定义序向组件（Se

18、quential Cell，如Flip-Flop、Latch等）所需的Setup Time，依据Clock上升或下降分为2类。 Hold Timing Arc：定义序向组件所需的Hold Time，依据Clock上升或下降分为2类。,Top-Level Implementation Steps,Run trial routing. Use the trial router to route the design. Examine the congestion map and the report to identify congested areas. Use the prototyping

19、option of Trial Route to gauge the routability of the design. Extract RCs. Fire & Ice QX ExtractionCreates Standard Parasitics Extraction File (SPEF). Analyze timing to find timing violations. Although timing at this stage is likely to have many violations, you can still discover useful information.

20、 Analyze the timing to determine how to alter the floorplan.,Top-Level Implementation Steps,Analyzing Crosstalk Encounter uses either native or standalone CeltIC to perform crosstalk analysis. CeltIC calculates delay to cross-coupling effects on each net and produces delays in the form of a standard

21、 delay format (SDF) file. This delay is backannotated to Encounter to incorporate delay due to crosstalk effects. Encounter uses NanoRoute to repair noise-on-delay violations using the following techniques: wire spacing, net ordering, layer selection, minimization of long parallel wires, and shieldi

22、ng. Run power analysis. Assuming that the netlist is clean, use the Encounter engine to run a power analysis, and then use the VoltageStorm power analyzer to run an IR drop analysis. At this point, the block is essentially complete and the rest of the steps involve creating various representations o

23、f the block to use during top-level implementation and chip assembly.,Top-Level Implementation Steps,Adding Filler Cells You can add filler cells at the end of the design cycle to fill all the gaps between standard cell instances. Filler cells can also provide decoupling capacitance to complete the power connections in t