第10章+存储器接口.ppt

1、CHAPTER 10 Memory Interface(存储器接口)(P. 332),目的（P. 332）,译码存储器地址，并利用译码器的输出选择不同的存储器器件。 确定存储器的地址范围。 解释如何将RAM和ROM与微处理器接口。,10-1 MEMORY DEVICES(存储器件)(P. 332),Memory Pin Connections(存储器引脚)(P. 333),FIGURE 10-1 A pseudo-memory component illustrating the address, data and control connections,10.1存储器件（P. 332）,基于

2、微处理器的计算机系统的内存包括以下两种存储器： 只读存储器（ROM），永久性地存储驻留在系统中的程序和数据，即使未接电源，其存储内容也不会改变，也被称为非易失性存储器。 ROM在计算机外被编程，且一般只能读出数据。存放系统软件和永久性系统数据。分为掩膜ROM、可编程只读存储器（PROM）、可擦除可编程只读存储器（EPROM）、快闪存储器（EEPROM）四种。 随机存取存储器（RAM），即读/写存储器，也被称为易失性存储器，在接通电源后正常操作下能够被重复读出、写入数据，但在没有电源的情况下它们不会保留数据。存放临时数据和应用软件。主要有静态RAM（SRAM）、动态RAM（DRAM）两种。,存储

3、器引脚,地址线 所有存储器件都有地址输入，用来选择存储器件中的一个存储单元。一个存储器件的地址线个数由其中的存储单元的数目决定；反之，存储单元的数目可由地址线的数目来推断。例如，1K个存储单元的存储器件有10个地址线（A0-A9），如果一个存储器件有11个地址线，则它有2048（2K）个内部存储单元。,数据线 通过数据线向存储器件输入数据以便存储，或从存储器件提取数据以便读出。例如，一个存储器件有8个I/O线（D0-D7），这意味着这个存储器件在它的每个存储单元中存储8位数据，这样的一个8位宽的存储器件常常被称为字节宽存储器。 存储器件的目录表通常用存储单元数乘以每单元的位数表示存储器件的规格

4、，例如，一个存储器件有1K存储单元，每单元存储8位数据，则制造商经常把它的规格写为1K X 8。,选择线 每个存储器件都有一个或几个输入信号用来选择或允许存储器件。这种输入信号常称为片选（CS）、片允许（CE）或选择（S）输入。 如果CE、CS或S输入有效（为逻辑0），则存储器件执行一次读或写操作。如果它是无效的（为逻辑1），则存储器件不能进行读或写操作。若存在不止一个选择线，则所有这些选择线都必须被激活，才可以读或写数据。,控制线 ROM通常只有一个控制输入，而RAM通常有一个或两个控制输入。 ROM上的控制输入通常是输出允许（OE）或是输出选通（G），它允许数据从ROM的输出数据线上流出。

5、若OE和选择输入CS均有效，则输出被允许；若OE无效，则输出被禁止。 RAM存储器件有一个或两个控制输入。若只有一个控制输入，它常被称为R/W。只有器件被选择输入（CS）选中时，该控制线选择一次读操作或写操作。若RAM有两个控制输入，通常被标为WE（或W）和OE（或G）。这里，WE（写允许）必须有效，才能执行一次存储器写操作，OE必须有效，才能执行一次存储器读操作。当这两个控制信号线（WE和OE）都存在时，它们不能同时有效；若两个控制输入均无效（逻辑1），则数据既不写入也不读出，数据线处于高阻抗状态。,例1,例2,38线译码器（74LS138）,10.2.4 双24线译码器（74LS139）,

6、Memory Reference(存储器接口),To interface memory to the microprocessor, there are generally four problems to be solved. Address Connections Data Connections Selection Connections Control Connections,Address Connections(地址线连接)(P. 344),The address connections include chip inner address connections and chip

7、 selection address connections. Chip inner address connections Connect the address connections of a memory chip with the microprocessor correspondingly. For example, the 2716 EPROM has 11 address ant the 8086/8088 microprocessor has 20. So address connections A10-A0 of 8086/8088 are connected to add

8、ress inputs A10-A0 of the EPROM.,Chip selection address connections When the 8086/8088 microprocessor is compared to the 2716 EPROM, a difference in the number of address connections is apparent-the EPROM has 11 address connections and the microprocessor has 20. There is a mismatch that must be corr

9、ected. If only 11 of the 8086/8088s address pins are connected to the memory, the 8086/8088 will see only 2K bytes of memory instead of the 1M bytes that it “expects” the memory to contain. The decoder corrects the mismatch by decoding the address pins that do not connect to the memory component. Th

10、e decoders outputs are connected to the chip selection or enable inputs of the memory.,Simple NAND Gate Decoder(简单的与非门译码器)(P. 344),EXAMPLE 10-1,A19,A18,A17,A16,A15,A14,A13,A12,A11,8088 数据 总线,A0,A10,O0,O7,CE,OE,FIGURE 10-13 A simple NAND gate decoder,2716,8088 地址 总线,D0-D7,0,Chip selection address con

11、nections,Chip inner address connections,Memory starting address,Memory ending address,Here, the 2K EPROM is decoded at memory address locations FF800H-FFFFFH.,The 3-to-8 Line Decoder (74LS138)(3-8线译码器)(P. 346),EXAMPLE 10-2,A0,A12,O0,O7,2764,OE,CE,CE,CE,CE,CE,CE,CE,CE,A,B,C,G2A,G2B,G1,A13,A14,A15,A16

12、,A17,A18,A19,D0-D7,0,0,0,1,2,3,4,5,6,7,1#,2#,3#,4#,5#,6#,7#,8#,138,8088 Address Bus,8088 Data Bus,Chip selection address connections,Chip inner address connections,Memory starting address,Memory ending address,Here, the 1# 2764 EPROM is decoded at memory address locations F0000H-F1FFFH.,The 2# 2764

13、EPROM is decoded at memory address locations F2000H-F3FFFH. The 3# 2764 EPROM is decoded at memory address locations F4000H-F5FFFH. The 4# 2764 EPROM is decoded at memory address locations F6000H-F7FFFH. The 5# 2764 EPROM is decoded at memory address locations F8000H-F9FFFH. The 6# 2764 EPROM is dec

14、oded at memory address locations FA000H-FBFFFH. The 7# 2764 EPROM is decoded at memory address locations FC000H-FDFFFH. The 8# 2764 EPROM is decoded at memory address locations FE000H-FFFFFH.,10-3 8088 MEMORY INTERFACE(8088和存储器接口)(P. 352),FIGURE 10-20,A0,A11,O0,O7,2732,OE,CE,CE,CE,CE,CE,CE,CE,CE,A,B

15、,C,G2A,G2B,G1,A12,A13,A14,A16,A17,A18,A19,8088 Address Bus,8088 Data Bus,0,1,2,3,4,5,6,7,1#,2#,3#,4#,5#,6#,7#,8#,A15,IO/M,+5V,138,WAIT,1K,F8000H-F8FFFH,F9000H-F9FFFH,FA000H-FAFFFH,FB000H-FBFFFH,FC000H-FCFFFH,FD000H-FDFFFH,FE000H-FEFFFH,FF000H-FFFFFH,164,QA,QB,QC,QD,QE,QF,QG,QH,CLK,CLR,CLK,CLK,1Tw,RD

16、Y1,AEN1,RDY2,WAIT,READY,8284A 时钟 产生器,8086 或 8088,READY,SI,1,FIGURE 9-17 A circuit that will cause between 0 and 7 wait states,QA,QB,QC,RDY1,CLK,T1,T2,T3,Tw,T4,10-4 8086 MEMORY INTERFACE(8086存储器接口)(P. 360),The 8086 microprocessor differ from the 8088 in three ways: The data bus is 16 bits wide instea

17、d of 8 bits wide as on the 8088. The IO/M pin of the 8088 is replaced with an M/IO pin. There is a new control signal called bus high enable.,The 16-bit data bus must be divided into two separate sections (banks) that are eight bits wide so that the microprocessor can write to either half (8-bit) or

18、 both halves (16-bit). One bank (low bank) holds all the even-numbered memory locations, and the other bank (high bank) holds all the odd-numbered memory locations. The data written to or read from the low bank are transferred through A0-A7, and the data written to or read from the high bank are tra

19、nsferred through A8-A15.,FIGURE 10-27 The high (odd) and low (even) 8-bit memory bans of the 8086 microprocessor,A0,TABLE 10-3 Memory bank selection using BHE and A0,Bank selection is accomplished in two ways： Separate decoders are used for each bank. A separate write signal is developed to select a

20、 write to each bank of the memory.,A0,1#,2#,FIGURE 10-28,High bank,Low bank,Specify the address range of the memory with an example of 1# and 2# memories.,Memory starting address,Memory ending address,Here, the 1# and 2# memory components are decoded at memory address locations 00000H-1FFFFH.,A 16-b

21、it memory decoder that places memory at locations 60000H-6FFFFH.,FIGURE 10-30,Example Interface 8088 microprocessor to Intel 2114 (1K*4) and Intel 2716 (2K*8) memory components to design a memory system composed of 1KB RAM and 4KB ROM. Plot the interface circuit and write down the address ranges of every memory component.,A0-A9,1# 2114,WE,CS,D0-D3,OE,CE,OE,62256,A0-A10,D0-D7,D0-D7,A0-A10,2#,D4-D7,CE,3#,4#,A,B,C,G2A,G2B,G1,A11,A12,A13,A15,A16,A17,A18,0,1,2,3,4,5,6,7,A14,IO/M,+5V,138,WAIT,1K