数据库 ch6_3m.ppt

1、未经作者允许，请勿发布该文档！,VHDL,Simulation ram_1 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(15 downto 8); ram_2 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(23 downto 16); ram_3 :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(31 downto 24); end generate ram32;,RAM

2、0,RAM1,RAM2,RAM3,8-bit Bus,8-bit Bus,8-bit Bus,8-bit Bus,32-bit Bus,8-bit addr,8-bit addr,8-bit addr,8-bit addr,Generate Example (2),ram32 : for i in 3 downto 0 generate ram :static_ram port map (cs_b,we_b,oe_b, abus(7 downto 0), dbus(8*i+7 downto 8*i); end generate ram32;,RAM0,RAM1,RAM2,RAM3,8-bit

3、Bus,8-bit Bus,8-bit Bus,8-bit Bus,32-bit Bus,8-bit addr,8-bit addr,8-bit addr,8-bit addr,Generate,Label: for ParameterName in Range generate ConcurrentStatements. end generate Label;,Label: if Condition generate ConcurrentStatements. end generate Label;,Generate Example (3),Adder,a(0)a(1)a(2)a(wid-1

4、) b(0)b(1)b(2)b(wid-1),sum(0)sum(1)sum(2)sum(wid-1)carry,HA,FA,FA,FA,a(0)b(0)c_in(1) a(1)b(1) c_in(2) a(2)b(2) c_in(3) c_in(win-1) a(wid-1)b(wid-1),sum(0) sum(1)sum(2) sum(wid-1) carry,Generate Example (4),adder : for i in 0 to wid-1 generate ls_bit : if i = 0 generatels_cell : HA port map (a(0), b(

5、0), sum(0), c_in(1);end generate lsbit; middle_bit : if i 0 and i wid-1 generatemiddle_cell : FA port map (a(i), b(i), c_in(i), sum(i), c_in(i+1);end generate middle_bit; ms_bit : if i = wid-1 generatems_cell : FA port map (a(i), b(i), c_in(i), sum(i), carry);end generate ms_bit; end generate adder;

6、,HA,FA,FA,FA,a(0)b(0)c_in(1) a(1)b(1) c_in(2) a(2)b(2) c_in(3) c_in(win-1) a(wid-1)b(wid-1),sum(0) sum(1)sum(2) sum(wid-1) carry,Agenda,Generate Assert Function Overloading FILE IO,Assert,Definition Label: assert Condition report StringExpression severity Expression; Note The message is written when

7、 the Condition is False! The default string for report clause is “Assertion violation” The default string for severity clause is “ERROR”,Concurrent Assertions ,Label : processbeginassert condition report error_string severity severity_value;wait sensitivity_clause ;end process Label;,concurrent asse

8、rtions,concurrent procedure calls,Assert Example (1),assert not (Reset = 0 and Set = 0) report R-S conflict severity Failure;,Assert Example (2),Severity_level,type severity_level is (note, warning, error, failure); (In standard.vhd),Agenda,Generate Assert Function Overloading FILE IO,Function Overl

9、oading,VHDL allows two subprograms to have the same name, provided the number or base types of parameters differs,Function Overloading (Example 1),function Foo(value : bit) return boolean; function Foo(value : std_logic) return boolean;,Function Overloading (Example 2),function + (arg1, arg2 : STD_L

10、OGIC_VECTOR) return STD_LOGIC_VECTOR; function + (L, R: UNSIGNED) return UNSIGNED; function + (L, R: SIGNED) return SIGNED;,Function Overloading (Example 3),FUNCTION + (arg1, arg2 :STD_LOGIC_VECTOR) RETURN STD_LOGIC_VECTOR IS CONSTANT ml : INTEGER := maximum(arg1length,arg2length); VARIABLE lt : STD

11、_LOGIC_VECTOR(1 TO ml); VARIABLE rt : STD_LOGIC_VECTOR(1 TO ml); VARIABLE res : STD_LOGIC_VECTOR(1 TO ml); VARIABLE carry : STD_LOGIC := 0; VARIABLE a,b,s1 : STD_LOGIC; - Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD ; BEGIN lt := zxt( ar

12、g1, ml ); rt := zxt( arg2, ml ); FOR i IN resreverse_range LOOP a := lt(i); b := rt(i); s1 := a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END;,FUNCTION + (arg1, arg2:UNSIGNED) RETURN UNSIGNED IS CONSTANT ml : INTEGER := maximum(arg1length,arg2length); VAR

13、IABLE lt : UNSIGNED(1 TO ml); VARIABLE rt : UNSIGNED(1 TO ml); VARIABLE res : UNSIGNED(1 TO ml); VARIABLE carry : STD_LOGIC := 0; VARIABLE a,b,s1 : STD_LOGIC; - Unsigned arithmetic addition of two vectors. MSB is Left. ATTRIBUTE synthesis_return OF res:VARIABLE IS ADD ; BEGIN lt := zxt( arg1, ml );

14、rt := zxt( arg2, ml ); FOR i IN resreverse_range LOOP a := lt(i); b := rt(i); s1 := a + b; res(i) := s1 + carry; carry := (a AND b) OR (s1 AND carry); END LOOP; RETURN res; END;,Function Overloading (Example 4),function + (a, b : byte) return byte isbegin return int_to_byte(byte_to_int(a) + byte_to_

15、int(b);end +; X1000_0010 + X0000_FFD0 + (X1000_0010, X0000_FFD0),Agenda,Generate Assert Function Overloading FILE IO Text File Binary File,Read/Write Text File,12123122341 Awfe 011100010 -,Disk File,1001011011,Line variable,ReadLine(),Read(),Data Object,12123122341 Awfe 011100010 -,Disk File,1001011

16、011,Line variable,WriteLine(),Write(),Data Object,Read From Text File,Write To Text File,Read/Write Text File Steps,Step 1Define user data object, DataObj Step 2Define Line object, LineObj variable LineObj: line; Step 2Define TextFile object, FileObj file FileObject: text is in FileName; file FileOb

17、ject: text is out FileName; Step 4Read/Write Data Read readLine(FileObj, LineObj); read(LineObj, DataObj); Write Write(LineObj, DataObj); WriteLine(FileObj, LineObj);,Read/Write Text File (Example),library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity text_file_read is end text_file_

18、read; architecture text_file_read_a of text_file_read is begin process variable bv: bit_vector(3 downto 0); variable ln_in: line; variable ln_out: line; file file_in: text is in text1.dat; file file_out: text is out text2.dat; begin loop exit when endfile(file_in); readline(file_in, ln_in); read(ln_

19、in, bv); write(ln_out, bv); writeline(file_out, ln_out); end loop; wait; end process; end text_file_read_a;,1111 1010,text1.dat,1111 1010,text2.dat,Write Text File (Example 1),library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity text_file_write is end text_file_write; architecture t

20、ext_file_write_a of text_file_write is begin process variable ln: line; variable bv: bit_vector(3 downto 0); file out_file: text is out text1.dat; begin bv := 1111; write(ln, bv); writeline(out_file, ln); bv := 1010; write(ln, bv); writeline(out_file, ln); wait; end process; end text_file_write_a;,1

21、111 1010,text1.dat,Write Text File (Example 2),entity Write_File is end entity Write_File; architecture arch_Write_File of Write_File is signal A, B, C: Bit_vector(3 downto 0); begin A = 1100; B=0110; C=0101; Monitor: process use STD.TEXTIO.all; file F: TEXT is out c:test.txt; -VHDL87 variable L: LI

22、NE; begin WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait for 0 ns; WRITE (L, NOW, Left, 10); WRITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait for 1 ns; WRITE (L, NOW, Left, 10); WR

23、ITE (L, A, Right, 5); WRITE (L, B, Right, 5); WRITE (L, C, Right, 5); WRITELINE (F, L); wait; end process; end architecture arch_Write_File;,0 ns 0000 0000 0000 0 ns 1100 0110 0101 1 ns 1100 0110 0101,10 5 5 5,Agenda,Generate Assert Function Overloading FILE IO Text File Binary File,Read/Write Binar

24、y File,Step 1Define File Format (Store data type) DataType Step 2Define user data object, DataObj Step 3Define File object, FileObj file FileObject: DataType is in FileName ; file FileObject: DataType is out FileName; Step 4Define data length variable, Length Step 5Read/Write Data read(FileObj, Data

25、Type, Length); write(FileObj, DataObject);,Write Binary File,library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity file_write is end file_write;,architecture file_write_a of file_write is type bit_vec is file of bit_vector; file out_file: bit_vec is out F1.dat; begin process variable

26、 v: bit_vector(3 downto 0); begin v := 1101; write(out_file, v); wait for 100 ms; v := 0001; write(out_file, v); wait for 100 ms; v := 1111; write(out_file, v); wait for 100 ms; wait; end process; end file_write_a;,Read/Write Binary File,architecture file_read_a of file_read is type bit_vec is file

27、of bit_vector; file in_file: bit_vec is in F1.dat; file out_file: bit_vec is out F2.dat; begin process variable v: bit_vector(3 downto 0); variable len: natural:= 1; begin loop exit when endfile(in_file); read(in_file, v, len); write(out_file, v); wait for 100 ms; end loop; wait; end process; end fi

28、le_read_a;,library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity file_read is end file_read;,Definitions For Text File (1),package TEXTIO is - Type definitions for text I/O: type LINE is access STRING; - A LINE is a pointer to a STRING value. type TEXT is file of STRING; - A file of

29、variable-length ASCII records. type SIDE is (RIGHT, LEFT); - For justifying output data within fields. subtype WIDTH is NATURAL; - For specifying widths of output fields. - Standard text files: file INPUT: TEXT open READ_MODE is STD_INPUT; file OUTPUT: TEXT open WRITE_MODE is STD_OUTPUT; - Input rou

30、tines for standard types: procedure READLINE (file F: TEXT; L: out LINE); procedure READ (L: inout LINE; VALUE: out BIT; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BIT); procedure READ (L: inout LINE; VALUE: out BIT_VECTOR; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE:

31、 out BIT_VECTOR); procedure READ (L: inout LINE; VALUE: out BOOLEAN; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out CHARACTER; GOOD: out BOOLEAN);,Definitions For Text File (2),procedure READ (L: inout LINE; VALUE: out CHARACTER); pr

32、ocedure READ (L: inout LINE; VALUE: out INTEGER; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out INTEGER); procedure READ (L: inout LINE; VALUE: out REAL; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out REAL); procedure READ (L: inout LINE; VALUE: out STRING; GOOD: out BOOLEAN); procedure READ (L: inout LINE; VALUE: out STRING); procedure READ (L: inout LINE; VALUE: out TIME; GOOD: out BOOLEAN); procedure READ (L: inout LI