savin1笔记本图纸-2-2-纬创homa 3ghoma 3g_1_0530_1

1、54321SYSTEM DC/DCProject code:91.41601.00148.4I601.011TPS5112550PCB P/N REVISION:INPUTSOUTPUTSHOMA 3GBlock Diagram-1082045V_S5(7A)3D3V_S5(7A5V_AUX_S53D3V_AUX_S5DCBATOUTSYSTEM DC/DCSMSCEMC2102Mobile CPUPenrynTPS5112451DDINPUTSOUTPUTS371D05V_S0(16A)1D8V_S3(16A)Cable Dock4 Port USB RJ45 CRT/DVI-DConnec

2、torDCBATOUTLCD154, 5RT902652HOST BUS667/800/1066MHz1.05VDDR_VREF_S3 (1.2A)DDR21.8V_S3CantigaAGTL+ CPU I/FDDR Memory I/F INTEGRATED GRAHPICSLVDS, CRT I/F6,7,8,9,10,11SWITCH PI5C3257QECRT667/800M1H2,z13G913152HDMI19SWITCH PS8122QFN48GSPDIF/MIC in/Line in/Line outDVI3D3V_S02D5V_S0 (300mA)DDR2ACJack667/

3、800M1H2,z13PCIex16RT901852VGA Borad(MXM Connector)46441D8V_S31D5V_S0 (2.5A)X4 DMIC-Link0400MHzCHARGERMS/MS Pro/xD/MMC/SDLINE INBQ2475454CardBusPCI315 in 1INPUTSOUTPUTS40OZ711MZ030,31PCMCIA SLOT 35CHG_PWR18V 6.0ACCInt MICDCBATOUTICH9M6 PCIe ports PCI/PCI BRIDGE ACPI 2.04 SATA12 USB 2.0/1.1 ports ETHE

4、RNET (10/100/1000MbE)High Definition Audio LPC I/FSerial Peripheral I/FMatrix Storage Technology(DO) Active Managemnet Technology(DO)CodecALC2683840AZALIASPIBIOS2M Bits 42CPU DC/DCISL6266A49(DY)MIC InINPUTSOUTPUTS40VCC_CORE01.3V38ADCBATOUTLANTXFM33RJ4533SWITCH PI3L500ZFEXOP AMPG1454R39Giga LANBCM576

5、4MKMLG 32GFX DC/DCISL626340LAN53INT.SPKR1.5WINPUTSOUTPUTSDCBATOUT VCC_GFXCORE40Line Out01.3V6.5APCIe20,21,22,23(Robson2/3G)Mini Card36(No-SPDIF)MODEMMDC Card37Mini CardKedron a/b/g/n(WLAN)C Link1RJ1136BBPCB STACKUPLPC BUSTOP USBSPI BIOS(2MB)42LPCVCC SATAWKinBbCondMini USB Blue Tooth 26CameraDEBUGSHD

6、D SATAWPCE773LA0DGCONN.422541S GNDLaunchButtomSATAODD SATAFinger PrinterUSB4 Port16BOTTOM 2928Touch Pad 41INT. KB 4124USBMIC in/Line-out/Line-inAAWistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, R.O.C.TitleBLOCK DIAGRAMSize A2Document NumberRev-1HOMA 3GSheet 1Date: Frida

7、y, May 30, 2008of5654321New Card34PWR SW TPS223134CRT18CLK GEN.ICS 9LPRS3653AFunctionalBCICH9M IntegratedDECantiga chipset andICH9M I/O controllerPull-upICH9MStrapDefinitionsHubRev.1.5strappingconfigurationandPull-downResistorsICH9 EDS 642879 Rev.1.5page 92Montevina Platform Design guide 223390.5ICH

8、9 EDS 642879page 21844natll33SDgNOTE:1. All strap signals are sampled with respect to the leading edge of the (G)MCH Power OK (PWROK) signal.2. iTPM can be disabled by a Soft-Strap option in the Flash-decriptor section of the Firmware. This Soft-Strap is activated only after enabling iTPM via CFG6.O

9、nly one of the CFG10/CFG/12/CFG13 straps can be enabled at any time.2211Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,Taipei Hsien 221, R.O.C.TitleReferenceSize A3Document NumberRev-156HOMA 3GSheet 2Date: Friday, May 30, 2008ofABCDEPin NameStrap DescriptionConfigurationCFG2:0FSB Freque

10、ncy Select000 = FSB1067011 = FSB667010 = FSB800others = ReservedCFG4:3 CFG8 CFG15:14 CFG18:17ReservedCFG5DMI x2 Select0 = DMI x21 = DMI x4 (Default)CFG6iTPM Host Interface10= The iTPM Host Interface is enabled(Note2)The iTPM Host Interface is disalbed(default)CFG7Intel Management engine Crypto strap

11、0 = Transport Layer Security (TLS) cipher suite with no confidentiality1 = TLS cipher suite withconfidentiality (default)veCFG9 rPCIE Graphics Lane0 = Reverse Lanes,15-0,14-1 ect.1= Normal operation(Default):Lane Numbered in orderCFG10PCIE Loopback enable0 = Enable (Note 3)1= Disabled (default)CFG13

12、:12XOR/ALL00 = Reserve10 = XOR mode Enabled01 = ALLZ mode Enabled (Note 3)11 = Disabled (default)CFG16FSB Dynamic ODT0 = Dynamic ODT Disabled1 = Dynamic ODT Enabled (Default)CFG19DMI Lane Reversal1 = DMI DMI0 = Normal operation(Default): Lane Numbered in OrderReverse Lanesx4 modeMCH - ICH:(3-0,2-1,1

13、-2and0-3) x2 modeMCH - ICH:(3-0,2-1)CFG20Digital Display Port (SDVO/DP/iHDMI)Concurrent with PCIe0 = Only Digital Display Port1 or PCIE is operational (Default)=Digital display Port and PCIe areoperting simulataneously via the PEG portVO_CTRLDATASDVO Present0 =No SDVO Card Present (Default)1 = SDVO

14、Card PresentL_DDC_DATALocal Flat Panel (LFP) Present0 = LFP Disabled (Default)1= LFP Card Present; PCIE disabledSIGNALResistor Type/ValueCL_CLK1:0PULL-UP 20KCL_DATA1:0PULL-UP 20KCL_RST0#PULL-UP 20KDPRSLPVR/GPIO16PULL-DOWN 20KENERGY_DETECTPULL-UP 20KHDA_BIT_CLKPULL-DOWN 20KHDA_DOCK_EN#/GPIO33PULL-UP

15、20KHDA_RST#PULL-DOWN 20KHDA_SDIN3:0PULL-DOWN 20KHDA_SDOUTPULL-DOWN 20KHDA_SYNCPULL-DOWN 20KGLAN_DOCK#The GLANpull-up or pull-down active when configured for DOCK# functionality and determined by LAN contrGNT3:0#/GPIO55,53,51PULL-UP 20KGPIO20PULL-DOWN 20KGPIO49PULL-UP 20KLDA3:0#/FHW3:0#PULL-UP 20KLAN

16、_RXD2:0PULL-UP 20KLDRQ0PULL-UP 20KLDRQ1/GPIO23PULL-UP 20KPME#PULL-UP 20KPWRBTN#PULL-UP 20KSATALED#PULL-UP 15KSPI_CS1#/GPIO58/CLGPIO6PULL-UP 20KSPI_MOSIPULL-DOWN 20KSPI_MISOPULL-UP 20KSPKRPULL-DOWN 20KTACH_3:0PULL-UP 20KTP3PULL-UP 20KUSB11:0P,NPULL-DOWN 15KSignalUsage/When SampledCommentHDA_SDOUTXOR

17、Chain Entrance/ PCIE Port Config1 bit1, Rising Edge of PWROKAllows entrance to XOR Chain testing when TP3 pulled low.When TP3 not pulled low at rising edge of PWROK,sets bit1 of RPC.PC(Config Registers:offset 224h). This signal has weak internal pull-dowHDA_SYNCPCIE config1 bit0, Rising Edge of PWRO

18、K.This signal has a weak internal pull-down. Sets bit0 of RPC.PC(Config Registers:Offset 224h)GNT2#/ GPIO53PCIE config2 bit2, Rising Edge of PWROK.This signal has a weak internal pull-up.Sets bit2 of RPC.PC2(Config Registers:Offset 0224h)GPIO20ReservedThis signal should not be pulled high.GNT1#/ GPI

19、O51ESI Strap (Server Only) Rising Edge of PWROKESI compatible mode is for server platforms only. This signal should not be pulled low for desttop and mobile.GNT3#/ GPIO55Top-BlockSwap Override.Rising Edge of PWROK.Sampled low:Top-Block Swap mode(inverts A16 for all cycles targetinH BIOS space).Note:

20、 Software will not be able to clear the Top-Swap bit until the system is rebooted without GNT3# being pulled down.GNT0#: SPI_CS1#/ GPIO58Boot BIOS Destination Selection 0:1.Rising Edge of PWROK.Controllable via Boot BIOS Destination bit (Config Registers:Offset 3410h:bit 11:10). GNT0# is MSB, 01-SPI

21、, 10-PCI, 11-LPC.SPI_MOSIIntegrated TPM Enable, Rising Edge of CLPWROKSample low: the Integrated TPM will be disabled. Sample high: the MCH TPM enable strap is sampled low and the TPM Disable bit is clear, the Integrated TPM will be enable.GPIO49DMI Termination Voltage, Rising Edge of PWROK.The sign

22、al is required to be low for desktop applications and required to be high for mobile applications.SATALED#PCI Express Lane Reversal. Rising Edge of PWROK.Signal has weak internal pull-up. Sets bit 27 of MPC.LR(Device 28:Function 0:Offset D8)SPKRNo Reboot.Rising Edge of PWROK.If sampled high, the sys

23、tem is strapped to the No Reboot mode(ICH9 will disable the TCO Timer system reboot feature). The status is readable via the NO REBOOT bit.TP3XOR Chain Entrance. Rising Edge of PWROK.This signal should not be pull low unless using XOR Chain testing.GPIO33/ HDA_DOCK_EN#Flash Descriptor Security Overr

24、ide Strap Rising Edge of PWROKSampled low:the Flash Descriptor Security will be overridden. If high,the security measures will bein effect.This should only be enabled in manufacturi environments using an external pull-up resister.ABCDE1D05V_S03D3V_S0R2623D3V_S0210R0603-PAD3D3V_S03D3V_CLKGEN_S02 R263

25、 11 R2242 3D3V_48MPWR_S03D3V_CLKPLL_S02 R264 10R0603-PAD C3180R0603-PAD0R3-0-U-GPC339C326C310C311C338C303 C304C332C317C331C333C337C327C328DYDY08/5/23 -1443D3V_48MPWR_S03D3V_CLKGEN_S03D3V_CLKPLL_S0U22CL=20pF0.2pF61 CLK_CPU_BCLK 4CPUT0 CPUC0C308 SC27P50V2JN-2-GP60 CLK_CPU_BCLK# 4GEN_XTAL_INR248 2 DY1

26、10MR2J-L-GPGEN_XTAL_OUT1 2358 CLK_MCH_BCLK 6X1CPUT1_F1 R2422257 CLK_MCH_BCLK# 6X2CPUC1_FX40R0402-PAD54 CLK_PCIE_ICH 21CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8X-14D31818M-44GP53 CLK_PCIE_ICH# 21R253 2R251 21 33R2J-2-GP1 2K2R2J-2-GPC30712CLK481721 CLK48_ICH4,7 CPU_SEL0USB_48MHZ/FSLAGEN_XTAL_OUT_R2008/04/01 SB3

27、D3V_S0RN6851CLK_PCIE_NEW 34CLK_PCIE_NEW# 34SRCT7/CR#_F SRCC7/CR#_ESC27P50V2JN-2-GP82.30005.951502nd = 82.30005.8914521 PM_STPPCI#21 PM_STPCPU#PCI_STOP# CPU_STOP#4448 CLK_PCIE_MINI1 36SRCT6 SRCC647 CLK_PCIE_MINI1# 36PCLKCLK254673241 CLK_PCIE_LAN 32SRCT10 SRCC10PCLKCLK4 PCLKCLK53742 312,13,23 SMBC_ICH

28、CLK_PCIE_LAN# 32SCLK81612,13,23 SMBD_ICHSDATACR#_H CR#_G40SRCT11/CR#_H SRCC11/CR#_GSRCT9 SRCC93D3V_S0633921 CLK_PWRGD10KR2J-3-GP 2 DY 1R252 SRN10KJ-6-GPCK_PWRGD/PD#2008/04/01 SBRN6937 CLK_PCIE_PEG 46PCLKCLK31 2 383831 PCLK_O230 PCLK_PCM41 PCLK_KBC21 PCLK_ICHCLK_PCIE_PEG# 46 PCLKCLK0 8PCLKCLK17PCI0/C

29、R#_A PCI1/CR#_BPCLKCLK46 PCLKCLK51034 CLK_MCH_3GPLL 7SRCT45R2301 22R2J-2-GP PCLKCLK2 421135 42 PCLK_FWHCLK_MCH_3GPLL# 7PCI2/TMESRCC4DYPCLKCLK3 PCLKCLK412PCI3 PCI4/27_SELECT PCI_F5/ITP_ENSRN33J-7-GP1331CLK_PCIE_MINI2 36CLK_PCIE_MINI2# 362008/04/02 SBCLK_PCIE_SATA 20SRCT3/CR#_C SRCC3/CR#_DPCLKCLK51432

30、2008/04/08 SB2008/04/01 SB28 SRCT2/SATAT SRCC2/SATACCLK_ICH141229 CLK_PCIE_SATA# 20644,7 CPU_SEL1 FSLB/TEST_MODEPCLK_FWHEC32SC22P50V2JN-4GP10KR2J-3-GP CPU_SEL2_RUMA122R246R2332 154,7 CPU_SEL2REF0/FSLC/TEST_SEL DREFSSCLK_1 RN382DREFSSCLK_1#32425DREFSSCLK 7DREFSSCLK# 727MHZ_NONSS/SRCT1/SE127MHZ_SS/SRC

31、C1/SE2PCLK_ICHEC1292SC22P50V2JN-4GP1 33R2J-2-GPSRN0J-6-GP5514 21 CLK_ICH14NC#55RN37 SRN0J-6-GP PCLK_PCMEC1312SC22P50V2JN-4GP2008/04/11 SBDREFCLK_1 DREFCLK_1#12204DREFCLK 7DREFCLK# 7SRCT0/DOTT_96 SRCC0/DOTC_96213PCLK_KBCEC1302SC22P50V2JN-4GPUMACLK48_ICHEC1282SC22P50V2JN-4GPICS9LPRS365BKLFT-GP71.09365

32、.A032nd = 71.00875.A033D3V_S0EC35 SC22P50V2JN-4GP08/5/23 -122EMI capacitor for Antenna team suggestionRN70 SRN10KJ-6-GPDYICS9LPRS365YGLFT setting tablePIN NAMEDESCRIPTIONRN71PCLKCLK0 PCLKCLK1 1 2821 SATACLKREQ#7 CLK_MCH_OE#Byte 5, bit 70 = PCI0 enabled (default)7CR#_H CR#_G 3 4632 LAN_CLKREQ#46 MXM_

33、CLKREQ#PCI0/CR#_A1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pairSEL2 FSCSEL1 FSBSEL0 FSA5Byte 5, bit 60 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pairByte 5, bit 5CPUFSBDY SRN470J-3-GPPINNAMEDESCRIPTION100011100M133MX 533M0 = PCI1 enabled (default

34、)PCI1/CR#_B1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pairByte 5, bit 10 = SRC3 enabled (default)Byte 5, bit 40 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pairSRCC3/CR#_D1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pa

35、ir166M200M266M667M800M1067M000110100Byte 5, bit 00 = CR#_D controls SRC1 pair (default) 1= CR#_D controls SRC4 pairByte 6, bit 7PCI2/TME0 = Overclocking of CPU and SRC AllowedPCI3SRCC7/CR#_E0 = SRC7# enabled (default) 1= CR#_F controls SRC611PCI4/27M_SELByte 6, bit 61 = Pin17 as 27MHz, Pin 18 as 27M

36、Hz_SS, Pin13 as SRC-0, Pin14 as SRC-0#SRCT7/CR#_F0 = SRC7 enabled (default) 1= CR#_F controls SRC8Wistron Corporation21F, 88, Sec.1, Hsin Tai Wu Rd., Hsichih,PCI_F5/ITP_EN1 = ITP/ITP#Byte 6, bit 50 = SRC11# enabled (default) 1= CR#_G controls SRC9Taipei Hsien 221, R.O.C.SRCC11/CR#_GByte 5, bit 30 =

37、SRC3 enabled (default)TitleClock GeneratorDocument NumberSRCT3/CR#_C1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pairByte 6, bit 40 = SRC11 enabled (default) 1= CR#_H controls SRC10Byte 5, bit 20 = CR#_C controls SRC0 pair (default), 1= CR#_C controls SRC2 pairSRCT11/

38、CR#_HSizeRevHOMA 3GSheet-1Date: Friday, May 30, 20083of56ABCDESCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSC4D7U10V5ZY-3GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSCD1U16V2ZY-2GPSC4D7U10V5ZY-3GPSC1U16V3ZY-GPSC4D7U6D3V3KX-GP2 12 1212 12

39、 12 12 12 12 12 1181514169466223GND48 GNDPCI GNDREFVDDREF VDD48 VDDPCI VDDSRC VDDCPU VDDPLL3223036495926GND GNDSRC GNDSRC GNDSRC GNDCPU GND192743523356VDD96_IO VDDPLL3_IO VDDSRC_IO VDDSRC_IO VDDSRC_IO VDDCPU_IO65GND2 1567843212 12 12 12 1210 =SRC8/SRC8#0 = Pin17 as SRC-1, Pin18 as SRC-1#, Pin13 as D

40、OT96, Pin14 as DOT961 = Overclocking of CPU and SRC NOT allowedABCDE H_A#35.36 H_A#35.3H_DINV#3.0H_DINV#3.0 6 H_DSTBN#3.0CPU1A1 OF 4TP53 TPAD30H_DSTBN#3.0 6H_A#3 H_A#41D05V_S0H_DSTBP#3.0J4H1H_ADS# 6H_BNR# 6H_BPRI# 6H_DSTBP#3.0 6A3# A4# A5# A6# A7# A8# A9# A10# A11# A12# A13# A14# A15# A16#ADSTB0#ADS

41、# BNR# BPRI#L5E2H_A#5 H_A#6H_D#63.0L4G54H_D#63.0 64K5H_A#7 H_A#8M3H5H_DEFER# 6H_DRDY# 6H_DBSY# 6DEFER# DRDY# DBSY#R105 56R2J-4-GPN2F21H_A#9 H_A#10J1E1N3H_A#11 H_A#12P5F1H_BREQ#0 6 H_IERR#BR0#IERR# INIT#P2H_A#13D20L2H_A#14 H_A#15P4B3H_INIT# 20P1H_A#16R1H4H_LOCK# 6H_CPURST# 6,56LOCK#2 OF 4CPU1BM16 H_A

42、DSTB#0 6 H_REQ#4.0C1H_RS#2.0 6RESET# RS0# RS1# RS2# TRDY#H_REQ#0 H_REQ#1H_RS#0 H_RS#1H_D#0H_D#32 H_D#33K3F3 E22H_D#1Y22REQ0# REQ1# REQ2# REQ3# REQ4#D0# D1# D2# D3# D4# D5# D6# D7# D8# D9# D10# D11# D12# D13# D14# D15#DSTBN0# DSTBP0# DINV0#D32# D33# D34# D35# D36# D37# D38# D39# D40# D41# D42# D43# D

43、44# D45# D46# D47# DSTBN2# DSTBP2# DINV2#H2F4 F24H_D#2AB24H_REQ#2 H_REQ#3H_RS#2H_D#34 H_D#35K2G3 E26H_D#3V24J3G2H_D#4 G22V26H_TRDY#6H_REQ#4F23H_D#36 H_D#37L1V23H_D#5 H_D#6H_THERMDAG25G6T22H_HIT# 6H_HITM# 6HIT# HITM#H_A#17 H_A#18E25H_D#38 H_D#39Y2E4U25A17# A18# A19# A20# A21# A22# A23# A24# A25# A26#

44、 A27# A28# A29# A30# A31# A32# A33# A34# A35# ADSTB1#H_D#7 H_D#8E23U5U23H_A#19 H_A#20XDP_BPM#0 XDP_BPM#1TP29 TP32 TP27 TP33 TP30 TP31 TP34 TP43 TP37 TP38 TP39 TP58TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30 TPAD30C497 SC2200P50V2KX-2GPDYK24H_D#40 H_D#41R3AD4Y25BPM0#

45、BPM1# BPM2# BPM3# PRDY# PREQ# TCK TDI TDO TMS TRST# DBR#H_D#9 H_D#10G24W6AD3W22H_A#21 H_A#22XDP_BPM#2 XDP_BPM#3H_THERMDCJ24H_D#42 H_D#43U4AD1Y23H_D#11 H_D#12J23Y5AC4W24H_A#23 H_A#24XDP_BPM#4 XDP_BPM#5H22H_D#44 H_D#45U1AC2W25H_D#13 H_D#14R4AC1F26AA23H_A#25 H_A#26XDP_TCK XDP_TDIH_D#46 H_D#47T5AC5K22AA

46、241D05V_S0H_D#153T3AA6H23AB253H_A#27 H_A#28XDP_TDO XDP_TMSW2AB3J26Y26H_DSTBN#2 6H_DSTBP#2 6H_DINV#2 66 H_DSTBN#06 H_DSTBP#0 6 H_DINV#0W5AB5H26AA26H_A#29 H_A#30XDP_TRST# XDP_DBRESET#Y4AB6H25U22U2C20H_A#31 H_A#32R9868R2-GPV4H_D#16 H_D#17H_D#48 H_D#49W3N22AE24D16# D17# D18# D19# D20# D21# D22# D23# D24

47、# D25# D26# D27# D28# D29# D30# D31# DSTBN1# DSTBP1# DINV1#D48# D49# D50# D51# D52# D53# D54# D55# D56# D57# D58# D59# D60# D61# D62# D63# DSTBN3# DSTBP3# DINV3#THERMALPROCHOT# THRMDAH_A#33 H_A#34K25AA4AD24H_D#18 H_D#19P26H_D#50 H_D#51AB2AA21H_A#35R1220-GPR23AA3AB22CPU_PROCHOT#_R 49H_D#20 H_D#21R2J-2DYL23H_D#52 H_D#53V1A24 H_THERMDA 37H_THERMDC 37AB216 H_ADSTB#1M24B25 AC26THRMDCH_D#22 H_D#23L22H_D#54 H_D#55A6AD2020 H_A20M#20 H_FERR# 2