电子信息工程专业英语翻译清华出版社.ppt

Technical English,For Information Science and Electronic Engineering,Unit 2,Integrated Circuits,Part I,The Integrated Circuit,3,New Words,4,New Words,5,1,Digital logic and electronic circuits derive their functionality from electronic switches called transistor. Roughly speaking, the transistor can be likened to an electronically controlled valve whereby energy applied to one connection of the valve enables energy to flow between two other connections.1,由称为晶体管的电子开关得到它们的（各种）功能,粗略地说，晶体管好似一种电子控制阀，由此加在阀一端的能量可以使能量在另外两个连接端之间流动。,6,1,By combining multiple transistors, digital logic building blocks such as AND gates and flip-flops are formed. Transistors, in turn, are made from semiconductors. Consult a periodic table of elements in a college chemistry textbook, and you will locate semiconductors as a group of elements separating the metals and nonmetals.2,查阅大学化学书中的元素周期表，你会查到半导体是介于金属与非金属之间的一类元素。,7,1,They are called semiconductors because of their ability to behave as both metals and nonmetals. A semiconductor can be made to conduct electricity like a metal or to insulate as a nonmetal does. These differing electrical properties can be accurately controlled by mixing the semiconductor with small amounts of other elements.,可使半导体像金属那样导电，或者像非金属那样绝缘。,8,1,This mixing is called doping. A semiconductor can be doped to contain more electrons (N-type) or fewer electrons (P-type). Examples of commonly used semiconductors are silicon and germanium. Phosphorous and boron are two elements that are used to dope N-type and P-type silicon, respectively.3,N型硅半导体掺入磷元素，而P型硅半导体掺入硼元素。,9,2,A transistor is constructed by creating a sandwich of differently doped semiconductor layers. The two most common types of transistors, the bipolar-junction transistor (BJT) and the field-effect transistor (FET) are schematically illustrated in Figure 2.1.,图2.1给出了双极型晶体管和场效应晶体管的图示。,10,2,This figure shows both the silicon structures of these elements and their graphical symbolic representation as would be seen in a circuit diagram. The BJT shown is an NPN transistor, because it is composed of a sandwich of N-P-N doped silicon. When a small current is injected into the base terminal, a larger current is enabled to flow from the collector to the emitter.,它们用于电路图中的符号,当小电流注入基极时，可使较大的电流从集电极流向发射极。,11,2,The FET shown is an N-channel FET, which is composed of two N-type regions separated by a P-type substrate. When a voltage is applied to the insulated gate terminal, a current is enabled to flow from the drain to the source. It is called N-channel, because the gate voltage induces an N-channel within the substrate, enabling current to flow between the N-regions.,将电压加在绝缘的栅极上时，可使电流由漏极流向源极。,因为栅极电压诱导基底上的N通道，使电流能在两个N区域之间流动。,12,3,Another basic semiconductor structure shown in Figure 2.1 is a diode, which is formed simply by a junction of N-type and P-type silicon. Diodes act like one-way valves by conducting current only from P to N.,二极管的作用就像一个单向阀门，由于电流只能从P流向N。,13,3,Special diodes can be created that emit light when a voltage is applied. Appropriately enough, these components are called light emitting diodes, or LEDs. These small lights are manufactured by the millions and are found in diverse applications from telephones to traffic lights.,这种小灯泡数以百万计地被制造出来，有各种各样的应用，从电话机到交通灯。,14,4,The resulting small chip of semiconductor material on which a transistor or diode is fabricated can be encased in a small plastic package for protection against damage and contamination from the outside world.4,半导体材料上制作晶体管或二极管所形成的小芯片用塑料封装以防损伤和被外界污染。,15,4,Small wires are connected within this package between the semiconductor sandwich and pins that protrude from the package to make electrical contact with other parts of the intended circuit.,从封装内伸出以便与（使用该晶体管的）电路其余部分连接。,16,4,Once you have several discrete transistors, digital logic can be built by directly wiring these components together. The circuit will function, but any substantial amount of digital logic will be very bulky, because several transistors are required to implement each of the various types of logic gates.,任何实质性的数字逻辑（电路）都将十分庞大，因为要在各种逻辑门中每实现一种都需要多个晶体管。,17,5,At the time of the invention of the transistor in 1947 by John Bardeen, Walter Brattain, and William Shockley, the only way to assemble multiple transistors into a single circuit was to buy separate discrete transistors and wire them together. In 1959, Jack Kilby and Robert Noyce independently invented a means of fabricating multiple transistors on a single slab of semiconductor material.,购买多个分离的晶体管，将它们连在一起。,一种将多个晶体管做在同一片半导体材料上的方法,18,5,Their invention would come to be known as the integrated circuit, or IC, which is the foundation of our modern computerized world. An IC is so called because it integrates multiple transistors and diodes onto the same small semiconductor chip. Instead of having to solder individual wires between discrete components, an IC contains many small components that are already wired together in the desired topology to form a circuit.,IC包含按照形成电路所要求的拓扑结构连在一起的许多小元件，而无需再将分立元件的导线焊接起来。,19,6,A typical IC, without its plastic or ceramic package, is a square or rectangular silicon die measuring from 2 to 15 mm on an edge. Depending on the level of technology used to manufacture the IC, there may be anywhere from a dozen to tens of millions of individual transistors on this small chip.,每一边2mm至15mm的方形或矩形硅片,在这种小片上可能有几十个到几百万个晶体管,20,6,This amazing density of electronic components indicates that the transistors and the wires that connect them are extremely small in size. Dimensions on an IC are measured in units of micrometers, with one micrometer (1mm) being one millionth of a meter. To serve as a reference point, a human hair is roughly 100mm in diameter. Some modern ICs contain components and wires that are measured in increments as small as 0.1mm!,1微米是1米的百万分之一,21,6,Each year, researchers and engineers have been finding new ways to steadily reduce these feature sizes to pack more transistors into the same silicon area, as indicated in Figure 2.2.,22,7,When an IC is designed and fabricated, it generally follows one of two main transistor technologies: bipolar or metal-oxide semiconductor (MOS). Bipolar processes create BJTs, whereas MOS processes create FETs. Bipolar logic was more common before the 1980s, but MOS technologies have since accounted the great majority of digital logic ICs.,此后MOS技术在数字逻辑集成电路中占据了大多数,23,7,N-channel FETs are fabricated in an NMOS process, and P-channel FETs are fabricated in a PMOS process. In the 1980s, complementary-MOS, or CMOS, became the dominant process technology and remains so to this day. CMOS ICs incorporate both NMOS and PMOS transistors.,占主导地位的加工技术,Part II,Application Specific Integrated Circuit,25,New Words,26,New Words,27,New Words,28,1,An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. In contrast, the 7400 series and 4000 series integrated circuits are logic building blocks that can be wired together for use in many different applications.,而不是通用的,7400与4000系列集成电路是可以用导线连接的逻辑构建模块，适用于各种不同的应用,29,2,As feature sizes have shrunk and design tools improved over the years, the maximum complexity (and hence functionality) possible in an ASIC has grown from 5,000 gates to over 100 million.1,随着逐年来特征尺寸的缩小和设计工具的改进，ASIC中的最大复杂度从5000个门电路增长到了1亿个门电路，因而功能也有极大的提高。,30,2,Modern ASICs often include entire 32-bit processors, memory blocks including ROM, RAM, EEPROM, Flash and other large building blocks. Such an ASIC is often termed a SoC (System-on-Chip). Designers of digital ASICs use a hardware description language (HDL), such as Verilog or VHDL, to describe the functionality of ASICs.,现代ASIC常包含32位处理器，包括ROM、RAM、EEPROM、Flash等存储器，以及其它大规模组件。,31,3,Field-programmable gate arrays (FPGA) are the modern day equivalent of 7400 series logic and a breadboard, containing programmable logic blocks and programmable interconnects that allow the same FPGA to be used in many different applications. For smaller designs and/or lower production volumes, FPGAs may be more cost effective than an ASIC design.,7400系列和面包板的现代版,较小规模的设计或（与）小批量生产,32,3,The non-recurring engineering cost (the cost to setup the factory to produce a particular ASIC) can run into hundreds of thousands of dollars.2,不能循环的工程费用（建立工厂生产特定ASIC的成本）可能会达到数十万美元。,33,4,The general term application specific integrated circuit includes FPGAs, but most designers use ASIC only for non-field programmable devices and make a distinction between ASIC and FPGAs.3,专用集成电路这一通用名词也包括FPGA，但是大多数设计者仅将ASIC用于非现场可编程的器件，将ASIC和FPGA两者区别开来。,34,5 History,The initial ASICs used gate array technology. Ferranti produced perhaps the first gate-array, the ULA (Uncommitted Logic Array), around 1980. Customization occurred by varying the metal interconnect mask. ULAs had complexities of up to a few thousand gates. Later versions became more generalized, with different base dies customized by both metal and polysilicon layers. Some base dies include RAM elements.,多至几千个门电路的复杂度,适应用户的包含金属和多层硅的不同基底,35,6 Standard cell design,In the mid 1980s a designer would choose an ASIC manufacturer and implement their design using the design tools available from the manufacturer. While third party design tools were available, there was not an effective link from the third party design tools to the layout and actual semiconductor process performance characteristics of the various ASIC manufacturers.4,尽管有第三方设计工具，但第三方设计工具和不同的ASIC制造商的布线以及实际半导体工艺过程的性能之间却缺乏有效的联系。,36,6,Most designers ended up using factory specific tools to complete the implementation of their designs. A solution to this problem that also yielded a much higher density device was the implementation of Standard Cells. Every ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance and inductance; that could also be represented in third party tools.5,每个ASIC制造商都可创造他们自己的具有已知电性能的功能块，如传播延迟器、电容、电感，这些都可以用第三方工具来表示（实现）。,37,6,Standard cell design is the utilization of these functional blocks to achieve very high gate density and good electrical performance. Standard cell design fits between Gate Array and Full Custom design in terms of both its NRE (Non-Recurring Engineering) and recurring component cost.6,标准单元设计使门阵列和全定制设计之间在一次性投入的工程费用和循环元件成本方面相互适应。,Non-recurring engineering (NRE) refers to the one-time cost of researching, designing, and testing a new product.,38,7,By the late 1980s, logic synthesis tools, such as Design Compiler, became available. Such tools could compile HDL descriptions into a gate-level netlist. This enabled a style of design called standard-cell design. Standard-cell Integrated Circuits (ICs) are designed in the following conceptual stages, although these stages overlap significantly in practice.,标准单元集成电路的设计过程在概念上需经过以下几个过程，但事实上在实际生产中这些工序都有较大的重叠。,39,8,These steps, implemented with a level of skill common in the industry, almost always produce a final device that correctly implements the original design, unless flaws are later introduced by the physical fabrication process.7,以工业界普通的熟练水平实现的这些步骤几乎总是产生能正确实现原设计的最终器件，除非后来在物理制造过程中引入了缺陷。,40,9,A team of design engineers starts with a non-formal understanding of the required functions for a new ASIC, usually derived from requirements analysis.,对新的ASIC所要求功能的非正式理解,41,9,The design team constructs a description of an ASIC to achieve these goals using an HDL. This process is analogous to writing a computer program in a high-level language. This is usually called the RTL (register transfer level) design.,这一过程可类比于用高级语言编写计算机程序,42,9,Suitability for purpose is verified by simulation. A virtual system created in software, using a tool such as Virtutechs Simics, can simulate the performance of ASICs at speeds up to billions of simulated instructions per second.,以高达每秒数十亿条模拟指令的速度来模拟ASIC的功能,43,9,A logic synthesis tool, such as Design Compiler, transforms the RTL design into a large collection of lower-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized collections of gates such as 2 input nor, 2 input nand, inverters, etc.8,这些构成的元素是从一个标准单元库中得到的，这个库由事先规定好的门电路集合构成，例如2输入或非门，2输入与非门，非门等等。,44,9,The standard cells are typically specific to the planned manufacturer of the ASIC. The resulting collection of standard cells, plus the needed electrical connections between them, is called a gate-level netlist.,所产生的所有标准单元加上连接他们所需要的导线称为门级网表。,45,9,The gate-level netlist is next processed by a placement tool which places the standard cells onto a region representing the final ASIC. It attempts to find a placement of the standard cells, subject to a variety of specified constraints. Sometimes advanced techniques such as simulated annealing are used to optimize placement.,将标准单元布局在代表最终ASIC的区域,服从各种规定的约束,46,9,The routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Since the search space is large, this process will produce a “sufficient” rather than “globally-optimal” solution. The output is a set of photomasks enabling semiconductor fabrication to produce physical ICs.,由于搜索空间很大，该过程将产生满足充分条件的解，而不是全局最优解。,47,9,Close estimates of final delays, parasitic resistances and capacitances, and power consumptions can then be made. In the case of a digital circuit, this will be further mapped into delay information. These estimates are used in a final round of testing. This testing demonstrates that the device will function correctly over all extremes of the process, voltage and temperature. When this testing is complete the photomask information is released for chip fabrication.,这一测试表明器件将在所有极端的过程、电压、温度下正常工作。,48,10,These design steps (or flow) are also common to standard product design. The significant difference is that Standard Cell design uses the manufacturers cell libraries that have been used in hundreds of other design implementations and therefore are of much lower risk than full custom design.9,重要的差别在于标准单元设计使用制造商的单元库，这些库已用于数以百计的设计实现，因而比起全定制设计来风险小得多。,49,11 Gate array design,Gate array design is a manufacturing method in which the diffused layers, i.e. transistors and other active devices, are predefined and wafers containing such devices are held in stock prior to metallization, in other words, unconnected.10,门阵列设计是一种制造方法，事先定义好扩散层（晶体管和其它有源器件），包含这些器件的晶片在金属化之前被库存，就是说先不进行联接。,50,11,The physical design process then defines the interconnections of the final device. It is important to the designer that minimal propagation delays can be achieved in ASICs versus the FPGA solutions available in the marketplace. Gate array ASIC is a compromise as mapping a given design onto what a manufacturer held as a stock wafer never gives 100% utilization.11,门阵列ASIC是一种折中方案，因为将某一给定的设计与制造商库存的晶片相对应总是不可能达到100%利用率的。,51,12,Pure, logic-only gate array design is rarely implemented by circuit designers today, replaced almost entirely by field programmable devices such as FPGAs, which can be programmed by the user and thus offer minimal tooling charges, marginally increased piece part cost and comparable performance.12,现在电路设计者已经很少采用纯粹的逻辑门阵列设计，而几乎都代之以FPGA之类的现场可编程器件了。这些器件可由用户编程，使工具作业费用最低，以略为提高的零件价格获得可比的性能。,52,12,Today gate arrays are evolving into structured ASICs that consist of a large IP core like a processor, DSP unit, peripherals, standard interfaces, integrated memories SRAM, and a block of reconfigurable uncommitted logic.13,现在门阵列正在发展为结构化ASIC，其中包含很大的IP内核，如处理器、DSP单元、外围设备、标准接口、集成SRAM存储器、以及一组可重新设置的未确定功能的逻辑单元。,IP core (intellectual property core)：预先设计好，可复用，有知识产权的硬件或软件块,53,12,This shift is largely because ASIC devices are capable of integrating such large blocks of system functionality and “system on a chip” requires far more than just logic blocks.,片上系统所要求的（功能）比仅仅逻辑单元多得多,54,13 Full-custom design,The benefits of full-custom design usually include reduced area, performance improvements and also the ability to integrate analog components and other pre-designed components such as microprocessor cores that form a System-on-Chip.,减小的面积，性能的改进，以及集成模拟元件和其他预先设计的元件,55,13,The disadvantages can include increased manufacturing and design time, increased non-recurring engineering costs, more complexity in the CAD system and a much higher skill requirement on the part of the design team.14,缺点包括增加的制造和设计时间，增加的不可循环工程成本，更复杂的CAD系统，和对设计团队熟练程度高得多的要求。,56,13,However for digital only designs, “standard-cell” libraries together with modern CAD systems can offer considerable performance/cost benefits with low risk. Automated layout tools are quick and easy to use and also offer the possibility to manually optimize any perform