基于matlab和eda工具的数字滤波器(实验).ppt

Advanced Example,FPGA design techniques for a FIR filter,Outline,constant coefficient FIR filterIP based design flowoptimization for speed,area,powerEDA tools for the compilation process analysis and synthesis,数字滤波器,可以理解为是一个计算程序或算法，将代表输入信号的数字时间序列转化为代表输出信号的数字时间序列，并在转化过程中，使信号按预定的形式变化。数字滤波器有多种分类，根据数字滤波器冲激响应的时域特征，可将数字滤波器分为两种，即无限长冲激响应（IIR）滤波器和有限长冲激响应（FIR）滤波器。数字滤波器的功能是将一组输入的数字序列通过一定的运算后转变为另一组输出的数字序列，输入信号与系统函数通过线性卷积产生滤波输出。,数字滤波器可以用差分方程来表示，即数字滤波器的功能是将一组输入的数字序列通过一定的运算后转变为另一组输出的数字序列，输入信号与系统函数通过线性卷积产生滤波输出。数字滤波器可以用差分方程来表示，即用单位脉冲响应hn可以表示线性时不变离散系统，这时可以用卷积表示上式，如下：,线性时不变(LinearTime-Invariant，LTI)滤波器一般分为有限脉冲响应(Finite Impulse Response，FIR)滤波器和无限脉冲响应(Infinite Impulse Response，IIR)滤波器两类。FIR数字滤波器是一种非递归系统，其单位冲击响应是有限长序列，即其卷积过程是在有限个采样值中进行的。它的设计问题实质上是确定能满足所要求的转移序列或脉冲响应的常数问题，设计方法主要有窗函数法、频率采样法和等波纹最佳逼近法等。,带有常系数的FIR滤波器是一种线性时不变数字滤波器，其差分方程描述如下：,FIR系统的基本结构,有很多种，大致如下：(1) 直接型(2) 级联型(3) 快速卷积型(4) 线性相位(5) 频率取样型这些滤波器在实现结构上彼此之间有着较为紧密的继承和发展关系，而硬件实现方法没有本质上的差异，掌握一种滤波器的FPGA设计方法，只要理清其它类型滤波器的结构，就能很容易快速实现。,Seven-Tap Symmetrical FIR Filter,Six-Tap Symmetrical FIR Filter,直接型FIR滤波器结构图,实例,如上图所示的FIR滤波器，其中输入数据xn为宽度可以调节的有符号数，滤波器长度为5；系数为可以调节宽度的有符号数。yn=C0xn+C1xn-1+C2xn-2+C3xn-3+C4xn-4如图所示，为该滤波器具体实现时的结构，每一级的乘法或者加法都是并行的，而每一级之间都用寄存器予以隔离，使得每一级之间都是流水的，这种结构同时利用了并行和流水的思路，能够提高数据的吞吐率和滤波器的工作频率,分析,输入采样值x_in为8位有符号数，即数据在-128，127的范围内取值；系数C0，C1，C2，C3，C4同样为8位有符号数，在-128，127的范围内取值，此处波形对应的系数分别为1，-2，4，-2，1；实现的功能可用差分方程描述如下：yn=1xn+(-2)xn-1+4xn-2+(-2)xn-3+1xn-4当依次输入数据为，-1，-16，-36，-80.，输出对应为：-1，-14，-8，-70，167，-405；差分方程中xn，xn-1，xn-2，xn-3，xn-4对应x0，x1，x2，x3，x4;以第1个输出为例，此时，差分方程中xn-1，xn-2，xn-3，xn-4均为0，只有xn=-1;故易得第1个输出为-1；,FIR IP, Create a New Quartus II Project Launch IP Toolbench Step 1: Parameterize Step 2: Set Up Simulation Step 3: Generate,Design for speed,流水组合逻辑平衡赋值高扇出节点状态机优化模块边界输入输出寄存,Defaulted,195.35 MHz ( period = 5.119 ns )And resourcessee the report for detail,settings,New frequency,208.99 MHz ( period = 4.785 ns )跟设计、器件本身等诸多因素相关。此处速度提高资源？,Design for other targets,面积（area）resource sharing功耗(power),Methods,analysis,Report - Timing Analyzerlist paths-locate in last compilation floorplan-list path-Info:,Considerations,EDA toolsquartusDSE(design space explorer)synplifyFundamentallyoperation principle of FPGA, specific algorithms and architecture,Homework,Design for area.EDA tools settingprinciplesbook to readAdvanced FPGA Design: Architecture, Implementation, and Optimization Steve Kilts,Advanced FPGA Design: Architecture, Implementation, and Optimization,Product DescriptionThis book provides the advanced issues of FPGA design as the underlying theme of the work. In practice, an engineer typically needs to be mentored for several years before these principles are appropriately utilized. The topics that will be discussed in this book are essential to designing FPGAs beyond moderate complexity. The goal of the book is to present practical design techniques that are otherwise only available through mentorship and real-world experience.,Preface xiiiAcknowledgments xv1. Architecting Speed 11.1 High Throughput 21.2 Low Latency 41.3 Timing 61.3.1 Add Register Layers 61.3.2 Parallel Structures 81.3.3 Flatten Logic Structures 101.3.4 Register Balancing 121.3.5 Reorder Paths 141.4 Summary of Key Points 162. Architecting Area 172.1 Rolling Up the Pipeline 182.2 Control-Based Logic Reuse 202.3 Resource Sharing 232.4 Impact of Reset on Area 252.4.1 Resources Without Reset 252.4.2 Resources Without Set 262.4.3 Resources Without Asynchronous Reset 272.4.4 Resetting RAM 292.4.5 Utilizing Set/Reset Flip-Flop Pins 312.5 Summary of Key Points 34,3. Architecting Power 373.1 Clock Control 383.1.1 Clock Skew 393.1.2 Managing Skew 403.2 Input Control 423.3 Reducing the Voltage Supply 443.4 Dual-Edge Triggered Flip-Flops 443.5 Modifying Terminations 453.6 Summary of Key Points 464. Example Design: The Advanced Encryption Standard 474.1 AES Architectures 474.1.1 One Stage for Sub-bytes 514.1.2 Zero Stages for Shift Rows 514.1.3 Two Pipeline Stages for Mix-Column 524.1.4 One Stage for Add Round Key 524.1.5 Compact Architecture 534.1.6 Partially Pipelined Architecture 574.1.7 Fully Pipelined Architecture 604.2 Performance Versus Area 664.3 Other Optimizations 675. High-Level Design 695.1 Abstract Design Techniques 695.2 Graphical State Machines 705.3 DSP Design 755.4 Software/Hardware Codesign 805.5 Summary of Key Points 81,6. Clock Domains 836.1 Crossing Clock Domains 846.1.1 Metastability 866.1.2 Solution 1: Phase Control 886.1.3 Solution