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TheAT89C52isalowpower,highperformanceCMOS8bitmicrocomputerwith8KbytesofFlashprogrammableanderasablereadonlymemoryPEROM.ThedeviceismanufacturedusingAtmelshighdensitynonvolatilememorytechnologyandiscompatiblewiththeindustrystandard80C51and80C52instructionsetandpinout.TheonchipFlashallowstheprogrammemorytobereprogrammedinsystemorbyaconventionalnonvolatilememoryprogrammer.Bycombiningaversatile8bitCPUwithFlashonamonolithicchip,theAtmelAT89C52isapowerfulmicrocomputerwhichprovidesahighlyflexibleandcosteffectivesolutiontomanyembeddedcontrolapplications.TheAT89C52providesthefollowingstandardfeatures8KbytesofFlash,256bytesofRAM,32I/Olines,three16bittimer/counters,asixvectortwolevelinterruptarchitecture,afullduplexserialport,onchiposcillator,andclockcircuitry.Inaddition,theAT89C52isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePowerDownModesavestheRAMcontentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenexthardwarereset.AmapoftheonchipmemoryareacalledtheSpecialFunctionRegisterSFRspaceisshowninTable1.Notethatnotalloftheaddressesareoccupied,andunoccupiedaddressesmaynotbeimplementedonthechip.Readaccessestotheseaddresseswillingeneralreturnrandomdata,andwriteaccesseswillhaveanindeterminateeffect.Usersoftwareshouldnotwrite1stotheseunlistedlocations,sincetheymaybeusedinfutureproductstoinvokenewfeatures.Inthatcase,theresetorinactivevaluesofthenewbitswillalwaysbe0.ControlandstatusbitsarecontainedinregistersT2CONandT2MODforTimer2.TheregisterpairRCAP2H,RCAP2LaretheCapture/ReloadregistersforTimer2in16bitcapturemodeor16bitautoreloadmode.TheindividualinterruptenablebitsareintheIEregister.TwoprioritiescanbesetforeachofthesixinterruptsourcesintheIPregister.TheAT89C52implements256bytesofonchipRAM.Theupper128bytesoccupyaparalleladdressspacetotheSpecialFunctionRegisters.Thatmeanstheupper128byteshavethesameaddressesastheSFRspacebutarephysicallyseparatefromSFRspace.Whenaninstructionaccessesaninternallocationaboveaddress7FH,theaddressmodeusedintheinstructionspecifieswhethertheCPUaccessestheupper128bytesofRAMortheSFRspace.InstructionsthatusedirectaddressingaccessSFRspace.Forexample,thefollowingdirectaddressinginstructionaccessestheSFRatlocation0A0HwhichisP2.MOV0A0H,dataInstructionsthatuseindirectaddressingaccesstheupper128bytesofRAM.Forexample,thefollowingindirectaddressinginstruction,whereR0contains0A0H,accessesthedatabyteataddress0A0H,ratherthanP2whoseaddressis0A0H.MOVR0,dataNotethatstackoperationsareexamplesofindirectaddressing,sotheupper128bytesofdataRAMareavailableasstackspace.Timer0and1Timer0andTimer1intheAT89C52operatethesamewayasTimer0andTimer1intheAT89C51.Timer2Timer2isa16bitTimer/Counterthatcanoperateaseitheratimeroraneventcounter.ThetypeofoperationisselectedbybitC/T2intheSFRT2CONshowninTable2.Timer2hasthreeoperatingmodescapture,autoreloadupordowncounting,andbaudrategenerator.ThemodesareselectedbybitsinT2CON,asshowninTable3.Timer2consistsoftwo8bitregisters,TH2andTL2.IntheTimerfunction,theTL2registerisincrementedeverymachinecycle.Sinceamachinecycleconsistsof12oscillatorperiods,thecountrateis1/12oftheoscillatorfrequency.IntheCounterfunction,theregisterisincrementedinresponsetoalto0transitionatitscorrespondingexternalinputpin,T2.Inthisfunction,theexternalinputissampledduringS5P2ofeverymachinecycle.Whenthesamplesshowahighinonecycleandalowinthenextcycle,thecountisincremented.ThenewcountvalueappearsintheregisterduringS3P1ofthecyclefollowingtheoneinwhichthetransitionwasdetected.Sincetwomachinecycles24oscillatorperiodsarerequiredtorecognizea1to0transition,themaximumcountrateis1/24oftheoscillatorfrequency.Toensurethatagivenlevelissampledatleastoncebeforeitchanges,thelevelshouldbeheldforatleastonefullmachinecycle.CaptureModeInthecapturemode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN20,Timer2isa16bittimerorcounterwhichuponoverflowsetsbitTF2inT2CON.Thisbitcanthenbeusedtogenerateaninterrupt.IfEXEN21,Timer2performsthesameoperation,butalto0transitionatexternalinputT2EXalsocausesthecurrentvalueinTH2andTL2tobecapturedintoRCAP2HandRCAP2L,respectively.Inaddition,thetransitionatT2EXcausesbitEXF2inT2CONtobeset.TheEXF2bit,likeTF2,cangenerateaninterrupt.ThecapturemodeisillustratedinFigure1.AutoReloadUporDownCounterTimer2canbeprogrammedtocountupordownwhenconfiguredinits16bitautoreloadmode.ThisfeatureisinvokedbytheDCENDownCounterEnablebitlocatedintheSFRT2MODseeTable4.Uponreset,theDCENbitissetto0sothattimer2willdefaulttocountup.WhenDCENisset,Timer2cancountupordown,dependingonthevalueoftheT2EXpin.Figure2showsTimer2automaticallycountingupwhenDCEN0.Inthismode,twooptionsareselectedbybitEXEN2inT2CON.IfEXEN20,Timer2countsupto0FFFFHandthensetstheTF2bituponoverflow.Theoverflowalsocausesthetimerregisterstobereloadedwiththe16bitvalueinRCAP2HandRCAP2L.ThevaluesinRCAP2HandRCAP2Larepresetbysoftware.IfEXEN21,a16bitreloadcanbetriggeredeitherbyanoverfloworbyalto0transitionatexternalinputT2EX.ThistransitionalsosetstheEXF2bit.BoththeTF2andEXF2bitscangenerateaninterruptifenabled.SettingtheDCENbitenablesTimer2tocountupordown,asshowninFigure3.Inthismode,theT2EXpincontrolsthedirectionofthecount.Alogic1atT2EXmakesTimer2countup.Thetimerwilloverflowat0FFFFHandsettheTF2bit.Thisoverflowalsocausesthe16bitvalueinRCAP2HandRCAP2Ltobereloadedintothetimerregisters,TH2andTL2,respectively.Alogic0atT2EXmakesTimer2countdown.ThetimerunderflowswhenTH2andTL2equalthevaluesstoredinRCAP2HandRCAP2L.TheunderflowsetstheTF2bitandcauses0FFFFHtobereloadedintothetimerregisters.TheEXF2bittoggleswheneverTimer2overflowsorunderflowsandcanbeusedasa17thbitofresolution.Inthisoperatingmode,EXF2doesnotflaganinterrupt.BaudRateGeneratorTimer2isselectedasthebaudrategeneratorbysettingTCLKand/orRCLKinT2CONTable2.NotethatthebaudratesfortransmitandreceivecanbedifferentifTimer2isusedforthereceiverortransmitterandTimer1isusedfortheotherfunction.SettingRCLKand/orTCLKputsTimer2intoitsbaudrategeneratormode,asshowninFigure4.Thebaudrategeneratormodeissimilartotheautoreloadmode,inthatarolloverinTH2causestheTimer2registerstobereloadedwiththe16bitvalueinregistersRCAP2HandRCAP2L,whicharepresetbysoftware.TheTimercanbeconfiguredforeithertimerorcounteroperation.Inmostapplications,itisconfiguredfortimeroperationCP/T20.ThetimeroperationisdifferentforTimer2whenitisusedasabaudrategenerator.Normally,asatimer,itincrementseverymachinecycleat1/12theoscillatorfrequency.Asabaudrategenerator,however,itincrementseverystatetimeat1/2theoscillatorfrequency.Timer2asabaudrategeneratorisshowninFigure4.ThisfigureisvalidonlyifRCLKorTCLK1inT2CON.NotethatarolloverinTH2doesnotsetTF2andwillnotgenerateaninterrupt.Notetoo,thatifEXEN2isset,alto0transitioninT2EXwillsetEXF2butwillnotcauseareloadfromRCAP2H,RCAP2LtoTH2,TL2.ThuswhenTimer2isinuseasabaudrategenerator,T2EXcanbeusedasanextraexternalinterrupt.NotethatwhenTimer2isrunningTR21asatimerinthebaudrategeneratormode,TH2orTL2shouldnotbereadfromorwrittento.Undertheseconditions,theTimerisincrementedeverystatetime,andtheresultsofareadorwritemaynotbeaccurate.TheRCAP2registersmaybereadbutshouldnotbewrittento,becauseawritemightoverlapareloadandcausewriteand/orreloaderrors.ThetimershouldbeturnedoffclearTR2beforeaccessingtheTimer2orRCAP2registers.ProgrammableClockOutA50dutycycleclockcanbeprogrammedtocomeoutonP1.0,asshowninFigure5.Thispin,besidesbeingaregularI/0pin,hastwoalternatefunctions.ItcanbeprogrammedtoinputtheexternalclockforTimer/Counter2ortooutputa50dutycycleclockrangingfrom61Hzto4MHzata16MHzoperatingfrequency.ToconfiguretheTimer/Counter2asaclockgenerator,bitC/T2T2CON.1mustbeclearedandbitT2OET2MOD.1mustbeset.BitTR2T2CON.2startsandstopsthetimer.TheclockoutfrequencydependsontheoscillatorfrequencyandthereloadvalueofTimer2captureregistersRCAP2H,RCAP2L.Intheclockoutmode,Timer2rolloverswillnotgenerateaninterrupt.ThisbehaviorissimilartowhenTimer2isusedasabaudrategenerator.ItispossibletouseTimer2asabaudrategeneratorandaclockgeneratorsimultaneously.Note,however,thatthebaudrateandclockoutfrequenciescannotbedeterminedindependentlyfromoneanothersincetheybothuseRCAP2HandRCAP2L.UARTTheUARTintheAT89C52operatesthesamewayastheUARTintheAT89C51.InterruptsTheAT89C52hasatotalofsixinterruptvectorstwoexternalinterruptsINT0andINT1,threetimerinterruptsTimers0,1,and2,andtheserialportinterrupt.TheseinterruptsareallshowninFigure6.EachoftheseinterruptsourcescanbeindividuallyenabledordisabledbysettingorclearingabitinSpecialFunctionRegisterIE.IEalsocontainsaglobaldisablebit,EA,whichdisablesallinterruptsatonce.NotethatTable5showsthatbitpositionIE.6isunimplemented.IntheAT89C51,bitpositionIE.5isalsounimplemented.Usersoftwareshouldnotwrite1stothesebitpositions,sincetheymaybeusedinfutureAT89products.Timer2interruptisgeneratedbythelogicalORofbitsTF2andEXF2inregisterT2CON.Neitheroftheseflagsisclearedbyhardwarewhentheserviceroutineisvectoredto.Infact,theserviceroutinemayhavetodeterminewhetheritwasTF2orEXF2thatgeneratedtheinterrupt,andthatbitwillhavetobeclearedinsoftware.TheTimer0andTimer1flags,TF0andTFI,aresetatS5P2ofthecycleinwhichthetimersoverflow.Thevaluesarethenpolledbythecircuitryinthenextcycle.However,theTimer2flag,TF2,issetatS2P2andispolledinthesamecycleinwhichthetimeroverflows.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierthatcanbeconfiguredforuseasanonchiposcillator,asshowninFigure7.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdriven,asshowninFigure8.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadividebytwoflipflop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.ThecontentoftheonchipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Notethatwhenidlemodeisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecutionfromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.OnchiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toeliminatethepossibilityofanunexpectedwritetoaportpinwhenidlemodeisterminatedbyareset,theinstructionfollowingtheonethatinvokesidlemodeshouldnotwritetoaportpinortoexternalmemoryPowerDownModeInthepowerdownmode,theoscillatorisstopped,andtheinstructionthatinvokespowerdownisthelastinstructionexecuted.TheonchipRAMandSpecialFunctionRegistersretaintheirvaluesuntilthepowerdownmodeisterminated.Theonlyexitfrompowerdownisahardwarereset.ResetredefinestheSFRsbutdoesnotchangetheonchipRAM.TheresetshouldnotbeactivatedbeforeVCCisrestoredtoitsnormaloperatinglevelandmustbeheldactivelongenoughtoallowtheoscillatortorestartandstabilize.ProgramMemoryLockBitsTheAT89C52hasthreelockbitsthatcanbeleftunprogrammedUorcanbeprogrammed
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