实验五-数字时钟的设计

1、 实验五 数字时钟的设计实验性质：综合性 实验级别： 开课单位：信息与通信工程学院通信工程系 学时：4学时一、实验目的：1、学习用VHDL语言实现比较大型的电路的方法。 2、继续巩固cpld技术层次化设计方法。二、实验器材：计算机、Quartus II软件三、实验内容：设计一数字时钟，要求具有时、分、秒、计数显示功能，以24小时循环计时；具有清零，调节小时，分钟功能；具有整点报时功能。四、实验步骤：1、根据电路特点，用层次设计的概念，将此任务分成若干模块，规定每一模块的功能和各模块之间的接口。让几个学生分作和调试其中之一，然后再将各模块合起来联试。以培养学生之间的合作精神，同时加深层次化设计概

2、念。2、了解软件的元件管理深层含义，以及模块元件之间的连接概念，对于不同目录下的同一设计，如何融合。3、模块说明： 各种进制的计数及时钟控制模块（10进制、6进制、24进制） 扫描分时显示，译码模块 各模块都用VHDL语言编写五、实验模块：秒模块LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY second ISPORT(clk, reset,setmin : INSTD_LOGIC;enmin : OUTSTD_LOGIC;da0out: out std_logic_vector (

3、6 downto 0);END entity second;ARCHITECTURE fun OF second ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da0out = count; process ( clk , reset , setmin) begin - enmin=k; if (reset=0) then count = 0000000; elsif (setmin=0) then enmin = clk; elsif (clk event and clk=1) then if (count(3 downto 0)=1

4、001) then if (count 16#60#) then if (count=1011001) then enmin=1; count=0000000; ELSE count=count+7; end if; else count=0000000; end if; elsif (count 16#60#) then count = count+1; enmin=0 after 100 ns; else count=0000000; end if; end if; end process;END fun;分析： 脉冲从0计数至59，向前进1，enmin由低电平变至高电平。分模块LIBRA

5、RY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY minute ISPORT(clk, reset,sethour : INSTD_LOGIC;enhour : OUTSTD_LOGIC;da1out: out std_logic_vector (6 downto 0);END entity minute;ARCHITECTURE fun OF minute ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da1out = count; p

6、rocess ( clk , reset , sethour) begin - enmin=k; if (reset=0) then count = 0000000; elsif (sethour=0) then enhour = clk; elsif (clk event and clk=1) then if (count(3 downto 0)=1001) then if (count 16#60#) then if (count=1011001) then enhour=1; count=0000000; ELSE count=count+7; end if; else count=00

7、00000; end if; elsif (count 16#60#) then count = count+1; enhour=0 after 100 ns; else count=0000000; end if; end if; end process;END fun;分析： 脉冲从0计数至59，向前进1，enhour由低电平变至高电平。时模块LIBRARY ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY hour ISPORT(clk, reset,setweek : INSTD_LOGIC;

8、enweek : OUTSTD_LOGIC;da2out: out std_logic_vector (6 downto 0);END entity hour ;ARCHITECTURE fun OF hour ISSIGNAL count: STD_LOGIC_VECTOR( 6 downto 0);BEGIN da2out = count; process ( clk , reset , setweek) begin - enmin=k; if (reset=0) then count = 0000000; elsif (setweek=0) then enweek = clk; elsi

9、f (clk event and clk=1) then if (count(3 downto 0)=1001) then if (count 16#23#) then if (count=00100011) then enweek=1; count=0000000; ELSE count=count+7; end if; else count=0000000; end if; elsif (count 16#23#) then count = count+1; enweek=0 after 100 ns; else countyyyyyyyyyyyyyyyyyyyyyy=0000000; e

10、nd case; end process; end beh;分析： 将8421BCD码转化成7段码。 整点报时library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity speaker is port(clk:in std_logic; speaksec:in std_logic_vector(6 downto 0); speakmin:in std_logic_vector(6 downto 0); speak:out std_logic);end entity speaker;archite

11、cture fun of speaker isbeginprocess(clk,speakmin)begin if(clk event and clk=1)then if(speakmin=0000000 and speaksec=0000000)then speak=1;else speak=0;end if; end if;end process;end fun;分析： 当时钟计数到整点，即秒和分都等于0时蜂鸣器报警，以实现整点报时功能。输入：clk计数时钟信号，speaksec秒输出信号，speakmin分输出信号输出：报警信号输出转换模块六转一library IEEE;use IEEE

12、.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity sixtozero is Port ( d:in std_logic_vector(6 dow

13、nto 0); out6 : out std_logic; out5 : out std_logic; out4 : out std_logic; out3 : out std_logic; out2 : out std_logic; out1 : out std_logic; out0 : out std_logic); end sixtozero;architecture Behavioral of sixtozero isbeginprocess(d)Beginout6=d(6);out5=d(5); out4=d(4); out3=d(3); out2=d(2); out1=d(1);

14、 out0=d(0);end process;end Behavioral;二转一library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VCompone

15、nts.all;entity twotozero is Port ( d:in std_logic_vector(2 downto 0); out2 : out std_logic; out1 : out std_logic; out0 : out std_logic);end twotozero;architecture Behavioral of twotozero isbeginprocess(d)begin out2=d(2); out1=d(1); out0=d(0);end process;end Behavioral;3.三转一library IEEE;use IEEE.STD_

16、LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;- Uncomment the following lines to use the declarations that are- provided for instantiating Xilinx primitive components.-library UNISIM;-use UNISIM.VComponents.all;entity tretozero is Port ( d:in std_logic_vector(6 downto 0); out3 : out std_logic; out2 : out std_logic; out1 : out std_logic; out0 : out std_logic); end tretozero;architecture Behavioral of