算术逻辑单元英文演示文稿

算术逻辑单元英文演示文稿当前第1页\共有36页\编于星期二\12点（优选）算术逻辑单元英文当前第2页\共有36页\编于星期二\12点5.1ThevonNeumanncomputermodelThevastmajorityofcomputersystemsusedtodayareconstructedonthevanNeumanncomputermodel.Acomputerisviewedasastoredprogramcomputer.Aprogramisasequenceofinstructions,eachofwhichperformsabasicoperation.Beforeexecution,theprogramisstoredinmemoryalongwithdatatobemanipulated.Whenexecuted,theinstructionsinitareretrievedfrommemory,oneafteranother,andbroughtintotheprocessingunit.Decodesinstruction,retrievedata,performoperation,storesresultinregisterormemory.当前第3页\共有36页\编于星期二\12点Typicallyconsistsof3functionalblocks:acentralprocessingunit(CPU),mainmemory,aninput/outputsystem(I/O).ControlunitregistersALUCPUMainmemoryInput/OutputExternalBusThebasicorganizationofastored-programcomputer5.1ThevonNeumanncomputermodelInternalBus

当前第4页\共有36页\编于星期二\12点5.2ParallelfastaddersAnarithmeticunit(ALU)istheheartoftheCPUTheALUusuallyhasabinaryadderTheperformanceoftheALUismainlydeterminedbyitsadder.Weneedtodesignafastaddertogetridoftheexcessivecarry-propagationtimeoftheripple-carryadder.当前第5页\共有36页\编于星期二\12点DesignoffulladderFulladderwiththecarrybitCn-1.FnandCnaregivenasbelow: Fn＝XnYnCn-1+XnYnCn-1 +XnYnCn-1+XnYnCn-1 Cn＝XnYnCn-1+XnYnCn-1 +XnYnCn-1+XnYnCn-15.2Parallelfastadders当前第6页\共有36页\编于星期二\12点DesignoffulladderLogicmaps:Fn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1Cn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1FormedbytwohalfaddersFn:addresultofXn、YnandCn-1Fn=XnYnCn-15.2Parallelfastadders当前第7页\共有36页\编于星期二\12点DesignoffulladderAnbitaddercanbeproducedbyconnectingnfulladdersCarryistransferredserially,andFiiscalculatedwhenCi-1iscoming.Timeconsumedisdeterminedbynumberofbits.Asimple4bitsserialfulladder5.2Parallelfastadders当前第8页\共有36页\编于星期二\12点DesignofafastadderHowtoimprovethespeedofadder?ChangethepathwayofonebyonecarrybitsCn＝XnYnCn-1+XnYnCn-1+XnYnCn-1+XnYnCn-1

＝(Xn+Yn)Cn-1+XnYnThecarryofthefulladderoftheCidependsontheCi-1Althoughnfulladdersworkinparallel,thecarrysignalsaregeneratedandpropagatedinsequential.Theworst-caseofcarrypropagationoccurswhenacarrysignalpropagatesfromC0toCnallthewayalongthecarrypropagationcircuit.5.2Parallelfastadders当前第9页\共有36页\编于星期二\12点Carrylook-ahead（超前进位）ItreducessignificantlythecarrycreationtimebygeneratingthecarrysignalsforallthebitsatoncedirectlyfromtheinputcarryC0ThenatureofcarrypropagationC1isgeneratedaslongasoneofthesetwoconditionsismeeting：(1)BothofX1，Y1are“1”；(2)EitherofX1，Y1is“1”，andC0is“1”。ThenC1canbeexpressed：C1=X1Y1+(X1+Y1)C05.2Parallelfastadders当前第10页\共有36页\编于星期二\12点ThenatureofcarrypropagationC2isgeneratedaslongasoneofthefollowingconditionsissatisfied：(1)BothofX2and

Y2are“1”；(2)EitherofX2andY2is“1”，andX1andY1are“1”；(3)EitherofX2andY2is“1”，andeitherofX1andY1is“1”，withC0is“1”ThenC2canbeexpressed：C2=X2Y2

+(X2+Y2)X1Y1

+(X2+Y2)(X1+Y1)C05.2Parallelfastadders当前第11页\共有36页\编于星期二\12点ThenatureofcarrypropagationSimilarly，C3andC4canbecalculated：C3=X3Y3

+(X3+Y3)X2Y2

+(X3+Y3)(X2+Y2)X1Y1

+(X3+Y3)(X2+Y2)(X1+Y1)C0C4=X4Y4

+(X4+Y4)X3Y3

+(X4+Y4)(X3+Y3)X2Y2

+(X4+Y4)(X3+Y3)(X2+Y2)X1Y1

+(X4+Y4)(X3+Y3)(X2+Y2)(X1+Y1)C05.2Parallelfastadders当前第12页\共有36页\编于星期二\12点ThenatureofcarrypropagationCarrypropagatefunctionPiandcarrygeneratefunctionGi：

Gi=Xi·Yi carrygeneratefunction Pi=Xi+Yi carrypropagatefunction

Gi：whenXiandYiare“1”，nomatterwhetherthereislow-ordercarrybit，thecurrentcarrybitisgenerated.Pi：wheneitherofXiandYiis1，ifthereexistlow-ordercarrybit,thenCi-1ispropagatedtohigh-ordercarrybit5.2Parallelfastadders当前第13页\共有36页\编于星期二\12点ThenatureofcarrypropagationPutP1,G1intoC1～C4：

C1=G1+P1C0 （low-orderbit）

C2=G2+P2G1+P2P1C0 C3=G3+P3G2+P3P2G1+P3P2P1C0 C4=G4+P4G3+P4P3G2+P4P3P2G1+P4P3P2P1C05.2Parallelfastadders当前第14页\共有36页\编于星期二\12点ThenatureofcarrypropagationSincetheinputvariablestakeinvertedvalues,itsoutputgeneratestheinvertedvariables,“NAND”,“NOR”.“AND-OR-NOT”canbereadjustedas: Gi=Xi·Yi Gi=Xi·Yi=Xi+Yi carrygenerate Pi=Xi+Yi Pi=Xi+Yi=

Xi·Yi carrypropagate Gi·Pi=(Xi+Yi)·Xi·Yi=

Xi·Yi=Pi C1=G1+P1C0 C1=G1+P1C0=G1·P1C0=G1·(P1+C0)=G1·P1+G1·C0=P1+G1·C05.2Parallelfastadders当前第15页\共有36页\编于星期二\12点ThenatureofcarrypropagationC1=P1+G1C0 C2=P2+G2P1+G2G1C0 C3=P3+G3G2+G3G2P1+G3G2G1C0 C4=P4+G4P3+G4G3P2+G4G3G2P1+G4G3G2G1C05.2Parallelfastadders当前第16页\共有36页\编于星期二\12点5.2ParallelfastaddersThefour-bitcarrylook-aheadadder当前第17页\共有36页\编于星期二\12点5.2ParallelfastaddersTheblockcarrylook-aheadcircuitTheoreticallyspeaking,expressionC1~C4canbeexpandedtohigherorderbitsupton-1forn>4.However,asthebitnumberincreases,thenumberofproducttermsandmaximumnumberofliteralsinaproducttermintheexpressionwouldincreaseproportionally.Sowelimitthefan-inofanANDgateoranORgateto5.Themaximalallowablesizeofasingle-stagecarrylook-aheadcircuitis4bits.当前第18页\共有36页\编于星期二\12点5.2ParallelfastaddersTheblockcarrylook-aheadcircuit当前第19页\共有36页\编于星期二\12点5.2ParallelfastaddersTheblockcarrylook-aheadcircuit G’=G3+P3G2+P3P2G1+P3P2P1G0 P’=P3P2P1P074182

G3P3G2P2G1P1G0P0

G’P’C3C2C1C0当前第20页\共有36页\编于星期二\12点Theresultofcarrygeneratefunctionof74181Gis“1”aslongasoneoftheseconditionssatisfied：(1)BothofX3andY3are“1”，thatisG3=1；(2)EitherofX3andY3is“1”，andX2andY2areall“1”，thatisP3G2=1(3)EitherofX3andY3is“1”，andoneofX2andY2is“1”，andbothofX1andY1are“1”，thatisP3P2G1=1；(4)OneofX3andY3is“1”，andoneofX2andY2is“1”，andoneofX1andY1is“1”，andbothX0andY0are“1”，thatisP3P2P1G0=1。Therefore：

G=G3+P3G2+P3P2G1+P3P2P1G05.2Parallelfastadders当前第21页\共有36页\编于星期二\12点Therequirementstomeetgroupcarrypropagatefunctionof74181Pequals1is：EitherX3orY3is“1”，EitherX2orY2is“1”，EitherX1orY1is“1”，EitherX0orY0is“1”。Therefore：

P=P3P2P1P05.2Parallelfastadders当前第22页\共有36页\编于星期二\12点LetCn1,Cn2,Cn3(C3,C7,C11)bethecarrysofchip0tochip1,chip1tochip2andchip2tochip3.ReplaceG1,G2andG3byGN0,GN1,GN2.ReplaceP1,P2,P3byPN0,PN1,PN2.ReplaceC0byCn.ThenCn+x,Cn+y,Cn+ycanbegainedasfollows:

5.2Parallelfastadders当前第23页\共有36页\编于星期二\12点Theblockcarrylook-aheadcircuit16-bitfastaddersadderA15~A12B15~B1274182adderA11~A8B11~B8adderA7~A4B7~B4adderA3~A0B3~B0C0F3~F0G4P4C3G3P3C2G2P2C1G1P1F7~F4F11~F8F15~F12GPC05.2Parallelfastadders当前第24页\共有36页\编于星期二\12点5.3AnalysisofthedesignofacommercialALUchipALUcanimplementbasicarithmeticoperationsandlogicaloperations.Thissectionanalyzethedesignprocessofthecommercial4-bitsALUchipSN74181.当前第25页\共有36页\编于星期二\12点SN74181Logicmapsandfunctiontableof4-bitsALUS3S2S1S0PositivelogicM=HLogicopM=LarithmeticoperationCn=1Cn=0LLLLAAAadd1LLLHA+BA+B(A+B)add1LLHLA·BA+B(A+B)add1LLHH“0”Sub1“0”LHLLA·BAadd(A·B)Aadd(A·B)add1LHLHB(A·B)add(A+B)(A·B)add(A+B)add1LHHLABAsubBsub1AsubBLHHHA·B(A·B)sub1A·Å5.3AnalysisofthedesignofacommercialALUchip当前第26页\共有36页\编于星期二\12点SN74181S3S2S1S0PositivelogicM=HLogicopM=LarithmeticoperationCn=1Cn=0HLLLA+BAadd(A·B)Aadd(A·B)add1HLLHABAaddBAaddBadd1HLHLB(A·B)add(A+B)(A·B)add(A+B)add1HLHHA·B(A·B)sub1A·BHHLL“1”AaddAAaddAadd1HHLHA+BAadd(A+B)Aadd(A+B)add1HHHLA+BAadd(A+B)Aadd(A+B)add

1HHHHAAsub1AÅ5.3AnalysisofthedesignofacommercialALUchipLogicmapsandfunctiontableof4-bitsALU当前第27页\共有36页\编于星期二\12点1111000000000000000000G0=A0+B0=A0B0

P0=A0B0=A0+B0G0⊕P0=G0P0+G0P0

=(A0+B0)(A0+B0)

+(A0B0)(A0B0)=0+A0B0+A0B0+0+0=A0⊕B0当前第28页\共有36页\编于星期二\12点00000000A0B0C0ÅÅA1B1C1ÅÅ当前第29页\共有36页\编于星期二\12点SN74181Pinsof741815.3AnalysisofthedesignofacommercialALUchip当前第30页\共有36页\编于星期二\12点16-bitsALUFour74181circuitscanforms16-bitsALUFastcarryinchip,andonebyonebetweenchips.SoitwouldtakerelativelongtimetogenerateF0～F1516-bitsALUformedby4ALUchips5.3AnalysisofthedesignofacommercialALUchip当前第31页\共有36页\编于星期二\12点5.3AnalysisofthedesignofacommercialALUchip16-bitsALUTake4bitsasagroup.Usingmethodlike“4-bitcarrylook-aheadadder”toimplement16-bitsALU(formedby4ALUchips)，a16-bitfastALUcanbegained.74181

ALUcangenerateGn，Pn，then16-bitfastALUcanbeimplementedbyANDORNOTgatesand4ALUchips74182(Look-aheadcarryextender)canbegainedbyimplementinglogiccircuitofCn1、Cn2、Cn3当前第32页\共有36页\编于星期二\12点16-bitsfastALU16-bitfastALU74181A15~A12B15~B127418274181A11~A8B11~B874181A7~A4B7~B474181A3~A0B3~B0C0F3~F0G4P4C3G3P3C2G2P2C1G1P1F7~F4F11~F8F15~F12GPC05.3AnalysisofthedesignofacommercialALUchip当前第33页\共有36页\编于星期二\12点32-bitsfastALUTwo16-bit74182andeig