VHDL与数字集成电路设计VHDL3-1PPT演示课件

.,1,第三章 时序逻辑的设计优化,VHDL与数字集成电路设计,2 storage mechanisms, positive feedback, charge-based,.,2,锁存器：电平敏感,时序逻辑电路类型,寄存器：边沿敏感,D,Clk,Q,Clk,D,Q,D,Clk,Q,Clk,D,Q,.,3,锁存器类型,.,4,基于锁存器的设计,N latch is transparentwhen f = 0,P latch is transparent when f = 1,N,Latch,Logic,Logic,P,Latch,f,.,5,时间约束,t,CLK,t,D,t,c,2,q,t,hold,t,su,t,Q,DATA,STABLE,DATA,STABLE,Register,CLK,D,Q,.,6,正反馈与双稳态,.,7,双稳态,Gain should be larger than 1 in the transition region,.,8,基本锁存器电路,Converting into a MUX,Forcing the state(can implement as NMOS-only),.,9,多路选择器锁存器,Negative latch(transparent when CLK= 0),Positive latch(transparent when CLK= 1),CLK,.,10,具体电路,.,11,主从寄存器,Two opposite latches trigger on edgeAlso called master-slave latch pair,.,12,具体电路,Multiplexer-based latch pair,.,13,建立时间,.,14,降低时钟负载的主从寄存器,.,15,RS触发器,.,16,带有时钟控制的RS触发器,Cross-coupled NANDs,Added clock,.,17,不同的状态储存机制,D,CLK,CLK,Q,Dynamic (charge-based),Static,.,18,C2MOS寄存器,.,19,施密特触发器,VTC with hysteresisRestores signal slopes,.,20,CMOS施密特触发器,Moves switching thresholdof the first inverter,.,21,CMOS施密特触发器2,.,22,数据寄存器及相关电路,最快数据传递：时钟周期,.,23,数据寄存器及相关电路,最快数据传递时间：时钟周期,.,24,在输入端添加控制电路，构成其他类型的触发器,D触发器的控制与扩展,数据寄存器及相关电路,.,25,数据寄存器及相关电路,D触发器的控制与扩展,.,26,并行寄存与移位寄存,数据寄存器及相关电路,.,27,多功能移位寄存器,数据寄存器及相关电路,.,28,.,29,第四章 算数逻辑单元,4.1 加法器4.2 乘法器,VHDL与数字集成电路设计,.,30,加法器设计,加法运算从最低位开始，逐步向高位进行；每一位相加时，产生1位结果（s），同时产生1位进位（c）；最低位相加时，只需要考虑2个数据的相加：半加；其余位相加时，需要考虑3个数据的相加：全加。,4.1 加法器、算数逻辑单元,.,31,加法器设计,半加器,4.1 加法器、算数逻辑单元,.,32,加法器设计,全加器,4.2 加法器、算数逻辑单元,.,33,利用半加单元设计全加器,4.2 加法器、算数逻辑单元,.,34,可扩展的串行加法器： 采用全加器级联构成,4.2 加法器、算数逻辑单元,.,35,4位串行加法器：ASIC设计 第1级采用半加； 最高级取消进位。,4.2 加法器、算数逻辑单元,.,36,36,Full-Adder,.,37,37,The Binary Adder,.,38,38,Express Sum and Carry as a function of P, G, D,Define 3 new variable which ONLY depend on A, B,Generate (G) = AB,Propagate (P) = A,B,Delete =,A,B,Can also derive expressions for,S,and,C,o,based on,D and P,Propagate (P) = A,+,B,Note that we will be sometimes using an alternate definition for,.,39,39,The Ripple-Carry Adder,Worst case delay linear with the number of bits,Goal: Make the fastest possible carry path circuit,td = O(N),tadder = (N-1)tcarry + tsum,.,40,40,Complimentary Static CMOS Full Adder,28 Transistors,.,41,41,Inversion Property,.,42,42,Minimize Critical Path by Reducing Inverting Stages,Exploit Inversion Property,.,43,43,A Better Structure: The Mirror Adder,.,44,44,Transmission Gate Full Adder,.,45,45,Manchester Carry Chain,.,46,46,Manchester Carry Chain,.,47,47,Carry-Bypass Adder,Also called Carry-Skip,.,48,48,Carry-Bypass Adder (cont.),tadder = tsetup + Mtcarry + (N/M-1)tbypass + (M-1)tcarry + tsum,.,49,49,Carry Ripple versus Carry Bypass,.,50,50,Carry-Select Adder,.,51,51,Carry Select Adder: Critical Path,.,52,52,Linear Carry Select,.,53,53,Square Root Carry Select,.,54,54,LookAhead - Basic Idea,.,55,55,Look-Ahead: Topology,Expanding Lookahead equations:,All the way:,.,56,56,Logarithmic Look-Ahead Adder,.,57,57,Carry Lookahead Trees,Can continue building the tree hierarchically.,.,58,58,Tree Adders,16-bit radix-2 Kogge-Stone tree,.,59,59,Example: Domino Adder,Propagate,Generate,.,60,60,Example: Domino Adder,Propagate,Generate,.,61,.,62,第四章算数逻辑单元,4.1 加法器4.2 乘法器,VHDL与数字集成电路设计,.,63,8位乘法器设计：基于基本单元的扩展设计,2位乘法器：由1位乘法结果相加而成,成本：4+4+4 门时间：1+3,4.3 数据累加与乘法器设计,.,64,8位乘法器设计：基于基本单元的扩展设计,4位乘法器：由2位乘法结果相加而成,4个2位乘法器并行运算，产生4组数据，然后进行相加。,4.3 数据累加与乘法器设计,.,65,65,The Binary Multiplication,.,66,66,The Array Multiplier,.,67,67,The MxN Array Multiplier Critical Path,Critical Path 1 & 2,.,68,68,Carry-Save Multiplier,.,69,69,Multiplier Floorplan,.,70,70,Wallace-Tree Multiplier,.,71,71,Wallace-Tree Multiplier,.,72,72,The Binary Shifter,.,73,73,Th