微机原理ch058088,80286MICROPROCESSORSANDISABUS.doc

5 8088, 80286 MICROPROCESSORS AND ISA BUS5.1 8088 MICROPROCESSORThe first IBM PC used the 8088 microprocessor, and modern PCs still carry that legacy.The 8088 is a 40-pin microprocessor chip that can work in two modes:l minimum model maximum modeMaximum mode is used when we need to connect the 8088 to 8087 math coprocessor. If we do not need a math coprocessor, the 8088 is used in minimum mode.In 1978 Intel introduced the 16-bit microprocessor called 8086. It was 16-bit both internally and externally. The 8088 is internally identical to the 8086, but has only 8-bit external data bus. Since the original IBM PC introduced in 1981 used the 8088, we explore the 8088 instead of the 8086.图 51 The 8086 and 8088 in minimum mode5.1.1 Microprocessor busesEvery microprocessor-based system must have three sets of separate buses:l the address busl the data busl the control busThe address bus provides the path for the address to locate the targeted device, while the data bus is used to transfer data between the CPU and the targeted device. The control bus provides the signals to indicate the type of operation being executed, such as read or write.5.1.2 Data bus in 8088In the 图 51, pins 9-16 (AD0-AD7) are used both data and addresses in 8088.At the time of the design of the microprocessor in the late 1970s, due to IC chip packaging limitations, there was a great effort to use the minimum numbers of pins for external connections. Therefore, the designers multiplexed the address and the data buses, meaning that the Intel used the same pins to carry two sets of information: address and data. In the 8088, the address/data bus pins are named AD0-AD7, “AD” for “address/data”.ALE (address latch enable) pin signals whether the information on pins AD0-AD7 is address or data. Every time the microprocessor sends out an address, it activates (sets high) the ALE to indicate that the information on pins AD0-AD7 is the address (A0-A7). This information must be latched, then pins AD0-AD7 are used to carry data. When data is to be sent out or in, ALE is low, which indicates that AD0-AD7 will be used as data buses (D0-D7).This process of separating address and data from pins AD0-AD7 is called demultiplexing.5.1.3 Address bus in 8088The 8088 has 20 address pins (A0-A19), allowing to address a maximum of megabyte of memory.Pins of AD0-AD7 provide the A0-A7 address with the assistance of latch.To demultiplex the address signals from the address/data pins, a latch must be used to grab the address.The most widely used latch is the 74LS373 IC, see figures as the following.图 52 Role of ALE in address/data demultiplexing图 53 74LS373 D latchAD0 to AD7 of the 8088 go into the 74LS373 latch. ALE provides the signal for the latching action. For the 8088, the output of 74LS373 provides the 8-bit address A0-A7, while A8-A15 come directly from the microprocessor (pins 2-8 and pin 39). The last 4-bit address come from A16-A19, pin numbers 35-38.In any system, all addresses must be latched to provide a stable, high-drive-capability address bus for the system.图 54 Address, data, and control buses in 8088-based system5.1.4 8088 control busThere are many control signals associated with the 8088 CPU, however, for now we discuss those that with read and write operations.The 8088 can access both memory and I/O devices for read and write operations. Four control signals are:l MEMR (memory read)l MEMW (memory write)l IOR (I/O read)l IOW (I/O write)The 8088 provides three control signals: RD, WR, and IO/-M. The RD and WR pins are both active low. IO/-M is low for memory and high for I/O device. From these three pins, four control signals are generated: IOR, IOW, MEMR, MEMW, as shown in 图 54 and listed in 表 51.表 51 Control signal generationRDWRIO/-MSignal010-MEMR100-MEMW011-IOR101-IOW00xNever happens5.1.5 Bus timing of 8088The 8088 uses 4 clocks for memory and I/O bus activities. For example, in the read timing, ALE latches the address in the first clock.In second and third clock cycles, the read signal is provided.Finally, by the end of the fourth clock cycle the data must be at the pins of the CPU to be fetched.图 55 ALE TimingNotice that the entire read or write cycle time is only 4 clock cycles. If the task of reading or writing takes more than 4 clocks due to the slowness of memory or I/O devices, wait status (WS) can be requested from the CPU.5.1.6 Pins of 8088 in minimum modePins 24-32 of the 8088 have different function depending on whether the 8088 is used in minimum mode or maximum mode. Pin 24, -INTA (interrupt acknowledge)Active-low output signal.Informs interrupt controller that an INTR has occurred and that the vector number is available on the low 8 bines of the data bus. Pin 25, ALE (address latch enable)Active-high output signal.Indicates that a valid address is available on the external address bus. Pin 26, -DEN (data enable)Active-low output signal.Enables the data transceiver, such as 74LS245. This allows isolation of the CPU from the system bus. Pin 27, DT/-R (data transmit/receive)This signal is used to control the direction of data flow through the data transceiver (74LS245). Pin 28, IO/-M (input-output or memory)Indicates whether address bus is accessing memory or I/O device. In 8088, it is low when accessing memory and high when accessing I/O device. Pin 29, -WR (write)Active-low output signal.Indicates that the data on the data bus is being written to memory or I/O device. Pin 32, -RD (read)Active-low output signal.Indicates that the data on the data bus is being (brought in) from memory or I/O to the CPU Pin 31, HOLD (hold)Active-high input signal.This signal input from the DMA controller that indicates that the device is requesting access to memory and I/O space and that the CPU should release control of the local bus. Pin 30, HLDA (hold acknowledge)Active-high output signal.After input on HOLD, the CPU responds with HLDA to signal that the DMA controller can be used bus.5.1.7 Other 8088 pins Pin 33, MN/-MX (minimum/maximum)Minimum mode is selected by connecting MN/-MX directly to +5V; maximum mode is selected by grounding this pin. Pin 17, NMI (non-maskable interrupt)This is an edged-triggered (from low to high) input signal to processor that will make the microprocessor jump to the interrupt vector table after it finishes the current instruction. Pin 18, INTR (interrupt request)INTR is an active-high level-triggered input that is continuously monitored by the microprocessor for an external interrupt. This pin and INTA are connected to the 8259 interrupt controller chip. Pin 19, CLK (clock)Microprocessors require a very accurate clock for synchronization of events and driving the CPU. For this reason, Intel has designed the 8284 clock generator to be used with the 8088.CLK is an input and is connected to the 8284 clock generator. It acts as the heartbeat of the CPU Pin 22, READY (ready)READY is input signal used to insert a wait state for slower memories and I/O. It inserts wait states when it is low.The READY signal is needed to interface the CPU to low-speed memories and I/O devices. Pin 23, -TEST (test)In minimum mode this is not used. In maximum, however, this is an input from 8087 math coprocessor to coordinate communications between the two processors. Pin 21, RESET (reset)To terminate the present activities of the microprocessor, a high is applied to the RESET input pin. A presence of high will force the microprocessor to stop all activity and set major registers to the values shown in 表 52.表 52 IP and segment registers contents after resetRegisterContentsCSFFFFIP0000DS0000SS0000ES0000According to 表 52, when power is applied to the 8088, it wakes up at physical address FFFF0H, since a CS:IP address of FFFF:0000 leads to a physical address of FFFF0H. Therefore, we must have a non-volatile memory such as ROM at the FFFF0H address.5.2 8284 AND 8288 SUPPORTING CHIPSIn original IBM PC introduced in 1981 used the 8088 in maximum mode with a socket for the 8087 mat coprocessor. In maximum mode, the 8088 requires the use of 8288 to generate some control signals.Modern microprocessors such as Pentium have all these chips incorporated into a single chip.图 56 The 8086 and 8088 in maximum mode5.2.1 8288 bus controller图 57 8288 bus controllerAs shown in 图 57, the 8288 is the 20-pin chip specially designed to provide all the control signals when the 8088 is in the maximum mode. Input signals.1 -S0, -S1, -S2 (Status input)Input to these pins come from the 8088. Depending upon the input from the CPU, the 8288 will provide one of commands or control signals shown in 表 53.表 53 Status pins of the 8288S2S1S0Processor State8288 Command000Interrupt acknowledge-INTA001Read input/output port-IORC010Write input/output port-IOWC, -AIOWC011HaltNone100Code access-MRDC101Read memory-MRDC110Write memory-MWTC, -AMWTC111PassiveNone.2 CLK (clock)This is input from the 8284 clock generator, providing the clock pulse to the 8288 to synchronize all command and control signals with the CPU..3 -AEN (address enable)An active-low signal, activates the 8288 command output at least 115 ns after its activation. In the IBM PC it is connected to the AEN generation circuitry..4 CEN (command enable)An active-high signal is used to active/enable the command signals and DEN. In the IBM PC it is connected to the AEN generation circuitry..5 IOB (input/output bus mode)An active-high signal makes the 8288 operate in input/output bus mode rather than in system bus mode.Since the IBM PC is designed with system buses, it is connected to low. Output signals.1 -MRDC (memory read command)This is active-low and provides the MEMR (memory read) signal. It activates the selected device or memory to release its data to the data bus..2 -MWTC (memory write command), -AMWC (advanced memory write command)These two active-low signals are used to tell memory to record the data present on the data bus. These two are the same as the MEMW (memory write) signal, the only difference being that AMWC is activated slightly earlier in order to give extra time to slow devices..3 -IORC (I/O read command)This is an active-low signal that tells the I/O device to release its data to the data bus. In the PC it is called IOR (I/O read) control signal..4 -IOWC (I/O write command), -AMWC (advanced I/O write command)Both are active-low signals used to tell the I/O device to pick up the data on the data bus. AIOWC is available a little bit earlier to give sufficient time to slow devices. In the PC -IOWC is called IOW (I/O write) control signal..5 -INTA (interrupt acknowledge)An active-low signal will inform the interrupting device that its interrupt has been acknowledged and will provide the vector address to the data bus. In the IBM PC this is connected to INTA of the 8259 interrupt controller chip..6 DT/-R (data transmit/receive)DT/-R is used to control the direction of the data in and out of the 8088. In the IBM PC it is connected to DIR of the 74LS245. When the 8088 is writing data, this signal is high and will allow data go from the A side to the B side of the 74LS245, so that data is release to the system bus.Conversely, when the PC is reading data, this signal is low, which allows data to come in from the B side to the A side of the 74LS245 data transceiver chip, so that it can be received by the CPU. .7 DEN (data enable)An active-high signal will make the data bus either a local data bus or the system data bus. In the IBM PC it is used along with a signal from the 8259 interrupt controller to activate G of the 74LS245 transceiver..8 MCE/PDEN (master cascade enable/peripheral data enable)This is used along with the 8259 interrupt controller in master configuration.In the IBM PC the 8259 is used as a slave, therefore, this pin is ignored..9 ALE (address latch enable)ALE is an active-high signal used to activate address latches. The 8088 multiplexes address and data through AD0-AD7 in order to save pins. In the IBM PC, ALE is connected to the G input of the 74LS373, making demultiplexing of the addresses possible.5.2.2 8284 clock generatorThe 8284 is used in both minimum and maximum mode since it provides the clock and timing for the 8088-based system.图 58 8284 chipThis an 18-pin chip especially designed for use with 8088/86 microprocessor. Input pins.1 -RES (reset in)This is an input active-low signal to generate RESET. In the IBM PC, it is connected to the power-good (电源完好) signal from the power supply. When the power switch in the IBM PC is turned on, assuming that the power supply is good, a low signal is provided to this pin and the 8284 in turn will activate the RESET pin, forcing the 8088 to reset, then the microprocessor takes over. This called cold boot..2 X1 and X2 (crystal in)X1 and X2 are the pins to which a crystal is attached. The crystal frequency must be 3 times the desired frequency for the microprocessor. The maximum crystal for the 8284A is 24 MHz. The IBM PC is connected to a crystal of 14.31818 MHz..3 F/-C (frequency/clock)This pin provides an option for the way the clock is generated. If connected to low, the clock is generated by the 8284 with the help of a crystal oscillator. If it is connected to high, it expects to receive clocks at the EFI pin. Since the IBM PC uses a crystal, this pin is connected to low..4 EFI (external frequency in)External frequency is connected to this pin if F/-C has been connected to high.In the IBM PC this is not connected..5 CSYNC (clock synchronization)This is an active-high signal is used to allow several 8294 chips to be connected together and synchronized.The IBM PC uses only one 8284, therefore, this pin is connected to low..6 RDY1 and -AEN1RDY1 is active-high and -AEN is active-low. These are together to provide a ready signal to the microprocessor, which will insert a WAIT state to the CPU read/write cycle.In the PC, RDY1 is connected to DMAWAIT, -AEN1 is connected to RDY/WAIT. This allows a wait state to be inserted by either the CPU or DMA..7 RDY2 and -AEN2These function exactly like RDY1 and -AEN1 but are designed to allow for a multiprocessing system.In the IBM PC, RDY2 is connected to low, and -AEN2 is connected to high. .8 -ASYNCThis called ready synchronization select. An active low is used for devices that are not able a adhere to very strict RDY setup time requirement.In the IBM PC this is connected to low, making the timing design of the system easier with slower logic gates. Output signals.1 RESETThis is an active-high signal that provide a RESET signal to the 80.2.2 OSC (oscillator)This provides a clock frequency equal to the crystal oscillator and is TTL ( transistor - transistor logical) compatible.Since the IBM crystal oscillator is 14.31818 MHz, OSC will provide this frequency to the expansion slot of the IBM PC..3 CLK (clock)This is an output frequency equal to one-third of the crystal oscillator, or EFI input frequency, with a duty cycle (占空因数) of 33%. This is connected to the clock input of the 8088 and all other devices that must be synchronized with the CPU.In the IBM PC it is connected to pin 19 (CLK) of the 8088 microprocessor and other circuitry under the CLK88 label. This frequency, 4,772776 MHz (14,318318 divided by 3), is the processor frequency on which all of timing calculations of the memory and I/O cycle are based..4 PCLK (peripheral clock)PCLK is one-half of clock (or one-sixth of the crystal) with a duty cycle of 50% and is TTL compatible.In the IBM PC this is 2.386383 MHz is provided to the 8253 timer to be used to generate speaker tones, and for other functions..5 READYThis signal is connected to READY of the CPU.In the IBM PC it is connected to signal the 8088 that the CPU needs to insert a wait state due to the slowness of the devices that the CPU is trying to contact.5.3 8-BIT SECTION OF ISA BUSPrevious sections have explained the 8088 CPU and supporting chips. This section will explain how they are connected in the original IBM PC to produce the required buses to communicate with memory, input/output peripherals, and the 8-bit section of the ISA bus. The study of the 8-bit section is the main topic of this section.5.3.1 A brief of bus historyThe original IBM PC introduced in 1981 used an 8088 microprocessor, whose 8-bit data bus gave birth to the 8-bit section of the ISA bus. In 1984 when IBM introduced the IBM PC/AT using the 80286 microprocessor, the data bus was expanded to 16 bits. The 8-bit data bus can be seen as a subsection of the 16-bit ISA bus. Very often the 8-bit data bus was referred to as the IBM PC/XT (extended technology) bus in order to differentiate it from the IBM PC AT (advanced technology). Eventually the IBM PC AT bus became known as the ISA (Industry Standard Architecture) bus since the term “PC AT” was copyrighted by IBM. 5.3.2 Local bus vs. system busIn the discussion of PC design we often see the terms local bus and system bus. The system bus not only provides necessary signal to all the chips (RAM, ROM, and peripheral chips) on the motherboard, but also goes to the expansion slot for any plug-in expansion card. In contrast the local bus is connected directl