单片机外文翻译4.doc

外文文献翻译（译成中文1000字左右）：【主要阅读文献不少于5篇，译文后附注文献信息，包括：作者、书名（或论文题目）、出版社（或刊物名称）、出版时间（或刊号）、页码。提供所译外文资料附件（印刷类含封面、封底、目录、翻译部分的复印件等网站类的请附网址及原文）】外文文献：1. description the at89c52 is a low-power, high-performance cmos 8-bit microcomputer with 8k bytes of flash programmable and erasable read only memory(perom). the device is manufactured using atmels high density nonvolatile memory technology and is compatible with the industry standard 80c51 and 80c52 instruction set and pinout. the on-chip flash allows the program memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. by combining a versatile 8-bit cpu with flash on a monolithic chip, the atmel at89c52 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.2.features compatible with mcs-51 tm products 8k bytes of in-system reprogrammable flash memory endurance: 1,000 write/erase cycles fully static operation: 0 hz to 24 mhz three-level program memory lock 256 x 8-bit internal ram 32 programmable i/o lines.three 16-bit timer/counters eight interrupt sources programmable serial channel low power idle and power down modes the at89c52 provides the following standard features: 8k bytes of flash, 256 bytes of ram, 32 i/o lines, three 16-bit timer/counters， a six-vector two-level interrupt architecture,a full duplex serial port, on-chip oscillator, and clock circuitry. in addition, the at89c52 is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes.the idle mode stops the cpu while allowing the ram, timer/counters,serial port, and interrupt system to continue functioning. the power down mode saves the ram contents but feezes the oscillator, disabling all other chip functions until the next hardware reset.3. pin descriptionvccsupply voltage.gndground.port 0 port 0 is an 8-bit open drain bidrectional i/o port. as an output port, each pin can sink eight ttl mputs. when ls are written to port 0 pins, the pins can be used as high impedance inputs. port 0 can also be configured to be the multiplexed low order address/data bus during accesses to extemal program and data memory. in this mode, p0 has intemal pullups. port 0 also receives the code bytes during flash programming and outputs the de bytes during program verification. extemal pullups are required during program verification.port 1 port 1 is an 8-bit bidirectional 1/0 port with intemal pullups. the port 1 output buffers can sink/source four ttl inputs. when is are written to port 1 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 1 pins that are extemally being pulled low will source current (ill) because of the intemal pullups. 1n addition, p1.0 and p1.1 can be configured to be the timer/counter 2 extemal count input(p1.0/t2) and the timer/counter 2 trigger input (p1.1/t2ex), respectively，as shown in the following table. port 1 also receives the low-order address bytes during flash programing and verification.port 2 port 2 is an 8-bit bidirectional i/o port with internal pullups. the port 2 output buffers can sink/source four ttl inputs. when is are written to port 2 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 2 pins that are extemal1y being puiled low will source current (iil) because ofthe intemal pullups. port 2 emits the high-order address byte during fetches from extemal program memory and during accesses to extemal data memory that use 16-bit addresses (movx dptr). 1n this application, port 2 uses strong intemal pull-ups when emitting 1s. during accesses to external data memory that use 8-bit addresses (movx ri)， port 2 emits the contents of the p2 special function register. port 2 a1s0 receives the high-order address bits and some control signals during flash programming and verification.port 3 port 3 is an 8-bit bidirectional 1/0 port with internal pullups.be port 3 output buffers can sink/source four ttl inputs. when is are written to port 3 pins, they are pulled high by the internal pullups and can be used as inputs. as inputs, port 3 pins that are extemal1y being pulled low will source current (iil) because of the pullups. port 3 also serves the functions of various specia1 features of the at89c51, as shown in the following tab1e. port 3 also receives some contro1 signa1s for f1ash programming and verification.rst reset input. a high on this pin for two machine cycles while the osci1lator is running resets the device.aleiprog address latch enab1e is an output pu1se for 1atching the 10w byte of the address during accesses to externa1 memory. this pin is a1so the program pu1se input (prog) during f1ash programming. in norma1 operation, ale is emitted at a constant rate of 1/6 the oscillator frequency and may be used are externa1 timing or clocking purposes. note, however, that one ale port pin a1ternate functions p 1.0 t2 (externa1 count input to timer/counter 2),clock-out p1.1 t2ex (timer/counter 2 capture/re1oad trigger and direction control)port pin a1ternate functionsp3.0 rxd (seria1 input port) p3 .1txd (seria1 output port)p3.2 int0 (extema1 interrupt 0) p3.3 int1 (externa1 interrupt 1)p3.4 to (timer 0 externa1 input) p3.5 t1 (timer 1 externa1 input)p3.6 wr (extema1 data memory write strobe) p3.7 rd (externa1 data memory read strobe) pu1se is skipped during each access to externa1 data memory. if desired, ale operation can be disab1ed by setting bit 0 of sfr 10cation 8eh. with the bit set, ale is active on1y during a movx or movc instruction. otherwise, the pin is weak1y pulled high. setting the ale-disab1e bit has no effect if the microcontroller is in external execution mode.psen program store enab1e is the read strobe to externa1 program memory. when the at89c52 is executing code from externa1 program memory, psen is activated twice each machine cycle, except that two psen activations are skipped during each access to externa1 data memoryea/vppexternal access enab1e. ea must be strapped to gnd in order to enab1e the device to fetch code from extema1 program memory 10cations starting at 0000h up to ffffh. note, however, that if lock bit 1 is programmed, ea will be internally latched on reset. ea should be strapped to vcc for internal program executions. this pin a1so receives the 12-volt programming enable voltage (vpp) during flash programming when 12-volt programming is selected.翻译：at89c52是美国atmel公司生产的低电压高性能的coms8位单片机，内含8k字节可反复擦写的只读程序存储器perom)和256字节的随机存储数据存储器(ram)，器件采用atmel公司高密度，非易失性存储技术生产，与标准mcs-51指令系统和8052产品引脚兼容.片内内置8 位中央处理器(cpu)和flash 存储单元，功能强大的at89c52单片机适合许多较为复杂的控制场所.1. 主要性能参数:+与mcs-51系列产品兼容8kb 字节可重擦写flash闪存存储器1000 次写/擦除周期全静态操作:0到24m赫兹三级加密程序存储器256*8 字节内部ram32个可编程i/o口线3个16位计数1定时器8个中断源可编程串行uart通道低工耗空闲和掉电模式2. 功能特征概述 at89c52 提供以下标准功能:8kb字节flash闪存存储器，256*8字节内部ram，32个i/o口线，3个16位计数/定时器，一个6向量两级中断结构，一个全双工串行通信口，片内震荡器和时钟电路.同时at89c52 可以降到ohz静态逻辑操作，并支持两种软件可选的节电模式。空闲方式停止cpu工作，但允许ram，定时/计数器，传行通信口及中断系统继续工作。掉电方式保存ram 中的内容，但震荡器停止工作并禁止其它部件工作到下一个硬件复位。3. 引脚功能说明vcc: 电源电压gnd:地po口:po口是一组8位漏极开路型双响i/o口，也即地址/数据总线复口，作为输出口用时，每位能吸收电流的方式驱动8个ttl 逻辑门电路，对漏口p0写1时，可作高阻抗输入端用。在访问外部数据存储器或者程序存储器时，这组口线分时转换地址(低8位)和数据总线复用，在访问期间激活内部上拉电阻。在flash编程时，po口接收指令字节，而在程序校验时，输出指令字节，校验时要求外界电阻。p1口: p1是一个带内部上拉电阻的8 位双响i/o口，凹的输出缓冲级可驱动(吸收或输出电流)4个ttl 逻辑门电路，对端口写（1），通过内部的上拉电阻端口拉到高电平，此时可作输出入口。作输入口使用时，因为内部存在上拉电阻，某个号脚外部信号拉底时会输出一个电流。与at89c51不同之处是，p1.0和p 1. 1 还可分别作为定时器/计数器的外部输入(p1.0/t2)和输入( p1.lit2ex)。flash编程和程序检验期间，p1接收低8位地址。p1.0和p1.1的第二功能:p1.0/t2(定时/计数器2 外部技术脉冲输入1，时钟输出)p1.1 t2ex (定时/计数器捕获/重装载出发和方向控制)p2口: p2口是一个带内部上拉电阻的8位双响i/o口，凹的输出缓冲级可驱动(吸收或输出电流)4个ttl逻辑门电路，对端口写(1），通过内部的上拉电阻端口拉到高电平，此时可作输出入口。作输入口使用时，因为内部存在上拉电阻，某个引脚外部信号拉底时会输出一个电流。在访问外部程序存储器或16位地址的外部数据存储器(例如执行movxdptr 指令)时，p2口耸出高8位地址数据。在访问8位地址的外部数据存储器(如执行movxr1指令)时，p2口输出p2锁存器的内容。flash 编程和程序检验期间，p2口接收高位地址和一些控制信号。p3口: p3是一个带内部上拉电阻的8位双响i/o口，凹的输出缓冲级可驱动吸收或输出电流。4个ttl逻辑门电路，对端口写“1”，他们内部上拉电阻高并可作为输入端口。此时，别外部拉底的p3口将用上拉电阻输出电流。的口除了作为一般的vo 口外，更重要的用途是第二功能:p3.0 rxd 串行输入口 p3.1 txd 串行输出口p3.2 int0外部中断。 p3.3 intl 外部中断1p3.4 t0 定时/计数器。 p3.5 tl 定时/计数器lp3.6 wr 外部数据存储器写选通 p3.7 rd 外部数据存储器读选通此外，p3口还接收一些用于flash闪速存储器编程程序检验的控制信号。rst: 复位输入。当振荡器工作时，rst引脚出现两个机器周期以上高电平将使单片机复位。ale: 当访问外部数据存储器时，ale(地址锁存允许输出脉冲用锁存地址的低8位字节。一般情况下，ale以时钟振荡频率的116输出固定的脉冲信号， 因此它可以对外输出时钟或用于定时目得。要注意的是:每当访问外部数据存储器是将跳过一个ale脉冲。对flash 存储器编程期间，该引脚还用于输入编程脉冲(prog)。如有必要，可通过对特殊功能寄存器(sfr)区中的8eh单元的do位置，克尽职ale操作。该位置为后，只由一条movx 和movc指令才能将ale激活。此外，该引脚会被微弱拉高，单片机执行外部程序时，应设置ale禁止位无效。psen: 程序存储允许(psen) 输出是外部程序存储器的读选信号，当at98c刃有外部程序存储器指令(或数据肘，每个机器周期两次psen有效，即输出两个脉冲。在此期间，当访问外部数据存储器，将跳过两次psen信号。ea/vpp:外部访问允许，欲使cpu 仅访问外部数据存储器(地址为ooooh一f