外文翻译-----单片机数据采集接口.docx

附录二 外文原文及翻译 single-chip data acquisition interfacegintaras paukstaitisabstract this paper presents a single-chip data acquisition interface. its devoted for from one to eight analogous signals input to ram of ibm pc or compatible computers. maximal signal sampling rate is 80 khz. interface has programmable gain for analogous signals as well as programmable sampling rate and number of channels. some functional unit was designed using synthesis from vhdl with help of synopsys. interface was based on 1 mm cmos process from atmel-es2. it was verified using kit for dfwii of cadence. the place & route tools from cadence have been used to obtain the circuit layout. table of contains abstract 1. introduction 2. steps of designing 3. analogous part 4. digital part 5. interface testing 6. creation of layout 7. technical data 8. conclusions 9. acknowledgements 10. references 1. introduction nowadays units with vlsi are widely used in the world. it is really important for miniaturisation. circuits with some ic redesigned to vlsi reduce its area many times. by the way, relatively vlsi itself becomes cheaper. while using units with vlsi gets less damage, as well as uses less power. using of cad makes easier and faster complicated ic designing. cheaper computers give an opportunity to get servers not only for big companies and institutions of education but also for medium firms. this stride encouraged such complex circuits designing programs as synopsys and cadence creation. while using them it is possible to design suitable circuits for fabrication or layout creation. synopsys simulates functions described in vhdl and from its description synthesises circuits which can be made from cadence libraries elements. it abounds to transform them to cadence and to create the layout of ic. the steps of cadence designing are illustrated in fig. 1. single-chip data acquisition interface was designed according to basic circuit of data acquisition board. it was designed by department of applied electronics in kaunas university of technology. it is used in medicine. created single-chip interface has better electrical parameters. thats way it could be used wider. prototype board was designed in ttl element base. single-chip interface is designed in cmos element base. while converting the circuit there were no complicated problems. the delay of cmos elements is less than ttl. thats way the delay of signals was not bigger and didnt change the first work of the circuit. isa bus signals of ibm pc are ttl element logic levels, therefore interface should be connected through buffers for ttl and cmos logic levels reconciliation. 2. steps of designing a circuit was designed according to a basic circuit. that is way semi-custom design method was used. the flow-chart of interface is shown in the fig. 2. it was necessary to use 8 operational amplifiers (oa) to fit eight analogous signals to a/d converters limits. oa has programmable established gain. in many cases it could let analogous signal without any additional amplifiers to give to a/d converters. gain for every oa separately fixed with gain control block. two converters change analogous signal to the digital one. each of converters has 4 switch-able inputs. converters work method is comparison of every bit. channel control block establishes the order of signal switching. programmable interval timer establishes the frequency on signal switching as well as the data sampling rate. it has three counters, which work in frequency dividing and one-shot modes. dividing coefficients of timer is settings through internal bus. the length of dividing coefficient is 16 bits. the timer divides 894khz frequency signal therefore minimal interface sampling rate is fmin = 894 / 216 = 14 hz. maximal sampling rate limits speed characteristic of a/d converters. it is equal fmax = 80 khz. gain of oa, sampling rate and number of switching channels is set while sending charging words to the ports which are established by address decoding block. data to pc is fed in a single direct memory access (dma) mode. dma controller is in charge of commuting protocol from pc. dma control block is responsible from the side of interface. clock signal block sets clock frequency of 1,8 mhz for converters and 0,9 mhz for timer. control logic consists of simple gates and flip-flops. that is way gates and flip-flops of the es2 1mm cmos elements library was used to design it. the reason why the 1mm cmos es2 technology library was chosen was the wide choice of its analogous elements for semi-custom design. but es2 library has no some functional elements which were used in the circuit. for example intel 8253 programmable interval timer, binary counter or address decoder. therefore these elements was described in vhdl. while using elements of 1mm cmos es2 technology library with the assistance of synopsys necessary circuits ware synthesised. edif of circuits was transported to cadence. having been connected with the left control logic and with the analogous signals converting part they made a full functioning interface. the stages of designing are shown 3. analogous part alternating analogous voltage signals are changed to pulsate one from 0 to +5 v signal in the analogous part of interface. as converter is made of cmos elements and its power supply is 0 and +5 v so it can change only signal between 0 and +5 v limits. in order to reduce converting mistake converters are given analogous signal which should as close as possible to the limits. programmable oa makes stronger analogous signals. it has 16 possible gains which are selected with the help of four bit code. they have non-inverting input which has a pad for external analogous signal input. to change the alternating voltage ( 2,5 v) to pulsate one (0 to +5 v) virtual ground pad of oa is connected with +2,5 v and signal source ground (its ground voltage must be 2,5 v). design of interface was simulated with verilog-xl program. it simulates only digital signals. that is way while simulating analogous signals they were described as 8-bit digital vectors. verilog hdl models of analogous elements are used for this simulation. hdl models are changed into layout models for the creation of layout. a/d converter of es2 library is divided into 2 parts: analogous part consist of d/a converter and comparator. there is control logic and registers in the digital part. that is way only analogous part is changed in converters when layout is being created.4. digital part control block of interface was designed while changing discrete components of board to accordingly chip components of es2 library. some changes through different control of es2 library and prototype board analogous elements were made. it was timer described in vhdl for its designing. three models were created: two models for clock frequency dividing from coefficient which length is 16 and 8 bit and another one for one-shot mode. the length of control word is 8 bit. standard packages of ieee library were used for description of the models. it made easier operations themselves with vector data. vhdl models were simulated with synopsys vhdl debugger. functional correct vhdl models of timer counters were synthesised by using elements of es2 library. while synthesising optimisation was done. because the delay of circuits signal (few nanoseconds) is comparing with clock period (1,2 mm) is less so optimisation was only worth for small areas. set_max_area command was used for this goal. the area rapport summary of 16 bits timer counter synthesis is shown in the table 1. it is clear that a number of counters elements becomes smaller approximately for 13%. but their area becomes smaller only for 1,5%. the reason is that the number of elements was being diminished with diminishing of combinational logic. while element of combinational logic comparing with noncombinational one takes much small area. besides some elements often are changed by one with same function but not much small area, in example 2 or and 1 and element are changed to one or-and. while synthesising binary counter which purpose is dividing external clock signal for converters and timers were used commands which put buffers on output signals wires. it is done because clock signal is delivered for many flip-flops (on timer). primary synthesised circuit and a circuit with additional buffers and the number of diminished elements are shown in fig. 4. edif of synthesised functional elements was transported to cadence and there it is connected with control logic and analogous elements. table 1. summary of the counters area optimisation number of elements and their area before optimizationnumber of elements and their area after optimizationnumber of ports: number of nets: number of cells: number of references: combinational area: noncombinational area: total cell area:14 185 142 14 88935.203125 57934.800781 146870.000000number of ports: number of nets: number of cells: number of references: combinational area: noncombinational area: total cell area:14 175 124 16 86628.593750 57934.800781 144563.3906255. interface testing it was simulated full work for the verification of interface with verilog-xl. test programs are wrote in stl: control words fed for oa, channel control block and timer, data scanning. single-chip interface is good-working and has technical data as shown in table 2. 6. creation of layout analogous elements used in layout were changed from verilog hdl to physical. they are put on periphery of the chip. it is done because they have pads which are connected with ic packages pins. the pads of digital signals are put separately from analogous elements. the reason is that analogous elements have two power supply rails. and digital pads have four rails. corner elements witch supply powers for periphery pads have four rails too. therefore analogous elements are separated from corner elements by special elements. analogous power supply is given by these special elements for adc and oa. designer-guided automatic method was used for the creation of layout. it was used automatic standard logic placement and routing tools for cadence. to reduce the influence of noise region for standard logic was created as far as possible from the analogous elements part. analogous elements are connected among themselves outside ic. if the chip oa parameters are not sufficient it is possible to use outside placed oa. the layout of chip is shown in fig 5. chip has much empty area because its area is limited by pads of periphery. the total area is required is 21,5 mm2 (4,74,6 mm), with an active area of 1.6 mm2 (1,391,17 mm). 7. technical datanumber of inputs8input rangeac (0,1-2,0) vsignals resolution8 bitsmaximal sampling rate80 khzminimal sampling rate13 hzpower supply+ 5v8. conclusions in this paper i have presented a single chip analogous data acquisition interface. complex functional blocks was described in vhdl. with help of synopsys full functional unit was synthesised. units were excess, so the optimisation was done for small area. after transporting to cadence synthesised units were worked according to the set function. all circuits of interface, including models of analogous elements, were verified with verilog-xl. the chip layout based on 1.0 mm cmos process from atmel-es2 was created. my diploma thesis was based on this project. 9. acknowledgements thanks to prof. r.einauskas for his directing, dipl. eng. a.maiulis to give me a basic circuit of prototypic board and assoc. prof. r.beniseviit for they valuable suggestions. 10. references 1 data acquisition boards catalogue. kethler metrabyte, 1996-1997, vol. 28. 2 zanalabedin navabi. beginning vhdl: an introduction language concept, boston-massachusetts, 1994. 3 user guide for the es2 0.7mm/1.0mm cmos library design kit on cadence dfwii software (design kit/user guide version: 4.1e1), july, 1996.单片机数据采集接口摘要 本文提出了一种单芯片的数据采集接口。这是专门为从1到8通道的模拟信号输入到ram的ibm pc或兼容计算机。最大信号的采样率为80千赫。接口可编程增益为模拟的信号，以及可编程的采样率和声道数。一些职能单位的目的是利用合成的vhdl与帮助下， synopsys的。接口是基于1毫米cmos工艺向atmel -沙二段。这是核实使用试剂盒的dfwii cadence的。在布局布线工具，包括cadence被用来获取电路布局。 表中包含 摘要 1 导言 2 设计步骤 3 类似的部分 4 数字部分 5 接口测试 6 建立布局 7 技术数据 8 结论 9 鸣谢 10 参考资料 1 导言 现在单位，超大规模集成电路，广泛应用于世界各地。这是非常重要的小型化。一些ic电路重新设计，以减少其职权范围内的vlsi许多倍。顺便说一下，超大规模集成电路本身相对变得便宜。虽然与使用单位的vlsi得到较少的损害，以及使用较少的电力。利用cad技术使得更容易和更快的复杂的ic设计。廉价电脑提供一个机会让服务器不仅对大公司和教育机构，而且还为中型公司。这步鼓励这种复杂的电路设计程序synopsys和cadence的创造。虽然利用它们可以设计适当的集成电路制造或布局创造。 synopsys的模拟功能描述vhdl和其描述synthesises电路可以从cadence的图书馆内容。它处处把他们cadence和建立集成电路的布局。这些步骤是cadence的设计说明图。 1 。 单片机数据采集接口的目的是根据基本电路的数据采集板。这是设计部应用电子在考纳斯理工大学。这是用在医学。创建单芯片接口具有更好的电气参数。这是它可用于扩大。原型局的目的是在ttl元素基地。单片机接口的设计在cmos元件基地。虽然转换电路没有任何复杂的问题。延迟的cmos内容小于的ttl 。这是拖延的方式，信号并不大，并没有改变第一个工作的电路。 isa总线信号的ibm个人电脑是的ttl逻辑电平的因素，因此界面应通过缓冲器，可用于连接的ttl和cmos逻辑电平和解。 2 。设计步骤 电路的目的是根据一个基本电路。这是道路半定制设计方法。流图的界面中显示图2。有必要使用8运算放大器（办公自动化） ，以适应8个类似的信号， a / d转换器的限制。办公自动化系统已经建立了可编程增益。在许多情况下，它可以让类似的信号没有任何额外的放大器给a / d转换器。增益分别为每个办公固定增益控制块。两个转换器的信号，改变类似的数字之一。每个转换器有4个开关能够投入。转换器的工作方法是比较每位。通道控制块建立秩序的信号切换。 可编程间隔定时器规定频率对信号切换以及数据采样率。它有三个柜台，其中工作频率划分和一杆模式。划分系数的计时器设置通过内部总线。长度除以系数为16位。计时器划分894khz频率信号接口因此最小采样率是fmin =二百十六分之八百九十四= 14赫兹。最大采样率限制速度特性的a / d转换器。这是平等fmax = 80千赫。增益的办公自动化系统，采样率和一些交换渠道设置收费的话，而派遣的港口，所规定的地址译码座。数据，以pc是美联储在一个单一的直接内存访问（ dma ）模式。 dma控制器负责通勤议定书从pc 。的dma控制块负责从侧面的接口。时钟信号座台时钟频率为1.8 mhz的转换器和0,9兆赫的计时器。 控制逻辑包括简单盖茨和触发器。这是盖茨和方式触发器的沙二段1毫米的cmos元素的图书馆被用来设计它。为什么1毫米的cmos技术图书馆沙二段选择是多种可供选择的有类似内容半定制设计。但沙二段图书馆没有的一些功能性的因素中所使用的电路。例如，英特尔8253可编程间隔定时器，二进制计数器或地址解码器。因此，这些因素中描述的vhdl 。虽然使用的cmos内容一毫米图书馆沙二段技术的协助下， synopsys的必要电路陶瓷合成。 edif电路运到cadence的。经与左边的控制逻辑和类比信号转换的一部分，他们提出了全面运作的界面。设计阶段的显示 3 。模拟的部分 模拟的交流电压信号改为搏动一个从0到+5伏信号的一部分，模拟的界面。作为转换器的cmos是内容和它的电力供应是0及+5 v ，因此可以改变信号之间只有0及+5 v的限制。为了减少错误转换器转换得到模拟的信号，应尽可能接近极限。可编程办公自动化使强大模拟信号。它有16个可能的收益而被选中的帮助下， 4位代码。他们非反相输入有垫的外部模拟信号输入。若要变更交替电压（ 2,5五）搏动1 （ 0到5五） “虚拟地”垫的oa是与+2,5 v和信号源的“地面” （其“激励”电压必须是2,5五） 。接口设计是模拟的verilog仪程序。它只能模拟数字信号。这是类似的方法，而模拟信号，他们被描述为8位数字载体。 verilog hdl语言模型类似的内容，所用的模拟。高密度脂蛋白模式转变为布局模式的建立布局。 a / d转换器的沙二段图书馆分为两部分：一部分类似组成d / a转换器和比较。有控制逻辑和登记册中的数字部分。这是唯一的方式是模拟的一部分时，改变了转换器的布局正在形成。 4 。数字部分 控制模块的接口设计，同时变化