Quartus_II英文教程.ppt

Copyright 2005 Altera Corporation Designing with Quartus II Copyright 2005 Altera Corporation Objectives nCreate a New Quartus II Project nCompile a Design into an FPGA nLocate Resulting Compilation Information nAssign Design Constraints (Timing Restart Quartus II Window Recommend Using Top-Level File Name Select Working Directory Top-level Entity Does Not Need to Be the Same Name as Top-Level File Name File Menu Create a New Project Based on an Existing Project Hit Enter to Advance to Next Pin Change Names Constraints) lIndividual Entity/Node Controls nAccessed Using Assignments Menu nStored in QSF File 77 Copyright 2005 Altera Corporation Quartus Settings File (QSF) nStores All Settings Worst Fmax Is Listed on the Top Source, Destination Registers C Is Not nWhen Off, Paths A, B, Multicycle Hold = 2 (Default) CLK1 CLK2 PATH2 PATH1 DATA ARRIVAL WINDOW 203 Copyright 2005 Altera Corporation Multi-Cycle Hold Assignment nMinimum Point-to-Point Timing -Data Must Arrive after Hold Time -Used in Conjunction with a Multi-cycle Assignment CLK1 CLK2 MULTICYCLE MULTICYCLE HOLD CLK1 CLK2 Multicycle = 2 ; Multicycle Hold = 1 CLK1 CLK2 Multicycle = 3 ; Multicycle Hold = 1 (Note how the hold is applied) DATA ARRIVAL WINDOW 204 Copyright 2005 Altera Corporation Other Multi-Cycle Assignments nClock Enable Multi-Cycle -Assigns Multi-Cycle to Source of Clock Enable lI/O Pin lRegister nSource Multi-Cycle -Used When Source Clock is Higher Frequency 205 Copyright 2005 Altera Corporation Other Individual Timing Assignments nClassic FPGA Timing Assignments -Input (tsu, th) -Output (Max. & Min. tco) nCut Timing Path -Removes Paths from TDC & Timing Analysis -Specifies False Paths (Test Logic) nMax/Min Pin-to-Pin Delay (tpd) nMax/Min Point-to-Point Delay nReport Delay -Reports Delay between Selected Pins & Registers 206 Copyright 2005 Altera Corporation Assignment Types nSingle-Point -Constrains Paths from Data Pin to Any Register Fed by Any Clock nPoint-to-Point -Constrains Paths from Data Pin to Any Register Fed by Specified Clock nWildcard (* or ?) -Indicates All Targets with a Character or String l* - Zero or More Characters l? Single Character nTime Group -Assigns Named to User-Defined Group of Nodes -Allows Single Assignment to Constrain Entire Group 207 Copyright 2005 Altera Corporation Time Groups nAssigns Named to User-Defined Group of Nodes nAllows Single Assignment to Constrain Entire Group Members Exclude Members Create & Name Group Node Finder 208 Copyright 2005 Altera Corporation Making Timing Assignments Select Timing Category Choose Timing Assignment from the Drop-down List & Enter the Value Enter the Target or Destination Node Name Use Source Name (From) to Create a Point-to-Point Requirement Assignment Editor Is Used for All Individual Timing Assigments 209 Copyright 2005 Altera Corporation Other Timing Analyses nFast Corner Timing Analysis nEarly Timing Estimate 210 Copyright 2005 Altera Corporation Fast Corner Timing Analysis nUses Fastest (Best-Case) Timing Model nTwo Methods -Combined Fast/Slow Analysis Report lAssignments Timing Settings More Settings lNo List Paths on Fast Timing Report -Fast Analysis Only lProcessing Start Start Timing Analyzer (Fast Timing Model) lMust Re-Run Standard Timing Analysis Afterwards -Netlist Annotated with Minimum Values -Previous Standard Analysis Overwritten 211 Copyright 2005 Altera Corporation Combined Analysis Report 212 Copyright 2005 Altera Corporation Early Timing Estimate nPerforms Partial Compilation -Stops Fitter before Completion l80% Compilation Time Savings -Provides Early Placement Information lFloorplanning lLogicLock Regions nProvides Early Estimate on Design Delays -Full Static Timing Analysis Performed with all Timing Analyzer Features 213 Copyright 2005 Altera Corporation Early Timing Estimate nOptions -Realistic Estimated Delays Closest To Final Delays l0% Average Prediction Error (Within 10% of Full Fit) -Optimistic Estimated Delays Exceeds Final Delays l“Do I have any hope of meeting timing?” -Pessimistic Estimated Delays Falls Below Final Delays l“Am I almost guaranteed to meet timing?” 214 Copyright 2005 Altera Corporation Please go to Exercise 5 in the Exercise Manual 215 Copyright 2005 Altera Corporation Timing Assignment Exercise Summary nCreated Clock Settings nApplied Setting to Clock in Design nAssigned Timing Constraint to Input Pins nEnabled Physical Synthesis nAnalyzed Compiler Results in Technology Viewer 216 Copyright 2005 Altera Corporation nStandard/Single Clock Analysis nTiming Assignments -Global & Individual nFast Timing Model Analysis nEarly Timing Estimation Timing Analysis Summary 217 Copyright 2005 Altera Corporation Designing with Quartus II Simulation Copyright 2005 Altera Corporation Quartus II Simulation nSimulator Method & Features Overview nSimulator Settings nVWF File Creation nSimulation Output n3rd Party Simulation 219 Copyright 2005 Altera Corporation Supported Simulation Methods nQuartus II -VWF (Vector Waveform File) lPrimary Graphical Waveform File -VEC (Vector File) lText-Based Input File -SCF (Simulator Channel File) lMAX+PLUS II Graphical Waveform File -TBL (Table File) lText-Based Output File from Quartus II or MAX+PLUS II -Tcl/TK Scripting n3rd Party Simulators -Verilog/VHDL Testbench 220 Copyright 2005 Altera Corporation Simulator Features nConverts VWF into HDL Testbench nGenerates HDL Testbench Template nSupports Breakpoints nPerforms Automatically -Adding Output Pins to Output Waveform File -Checking Outputs at End of Simulation 221 Copyright 2005 Altera Corporation Simulator Settings nMode nInput File nPeriod nOptions Assignments Settings Simulator 222 Copyright 2005 Altera Corporation Simulator Mode nFunctional -Type: RTL -Uses Pre- Synthesis Netlist nTiming -Type: Gate- Level or Post- Place & Route -Uses Fully Compiled Netlist 223 Copyright 2005 Altera Corporation Simulator Input & Period nSpecifies Stimulus & Length of Simulation Period Enter End Time Run Simulation until End of Stimulus File Specify Stimulus File 224 Copyright 2005 Altera Corporation Simulator Options Reports Setup & Hold Violations Monitors & Reports Simulation for Glitches Reports Toggle Ratio Compares Simulation Outputs to Outputs in Stimulus File Automatically Add Output Pins to Simulation Generates Signal Activity File for PowerPlay Power Analyzer 225 Copyright 2005 Altera Corporation Create New Vector Waveform File nSelect File New Vector Waveform File (Other Files Tab) 226 Copyright 2005 Altera Corporation Insert Nodes nSelect Insert Node or Bus (Edit Menu) -VWF Must Be Open -Use Node Finder 227 Copyright 2005 Altera Corporation Specify End Time nMaximum Length of Simulation Time -Edit Menu 228 Copyright 2005 Altera Corporation Insert Time Bars Time Bar Specify Time Bar Set Master Time Bar nSet One Time Bar as Master nInsert Other Time Bars -Relative to Master -Absolute 229 Copyright 2005 Altera Corporation Draw Stimulus Waveform nHighlight Portion of Waveform to Change nOverwrite Value with Desired Value Overwrite Value Toolbar Shortcuts Highlight Waveform 230 Copyright 2005 Altera Corporation Overwrite Waveform Signal Values n1=Forcing 1 n0=Forcing 0 nX=Forcing Unknown nU=Uninitialized nZ=High Impedance nH=Weak 1 nL=Weak 0 nW=Weak Unknown nDC =Dont Care 231 Copyright 2005 Altera Corporation Overwrite Waveform Patterns nClock -Enter Period & Duty Cycle nCounting Pattern -Enter Count Timing -Enter Start Value & Increment nArbitrary (Group) Value nRandom Value 232 Copyright 2005 Altera Corporation nConverts VWF into HDL Testbench Waveform to Testbench Generator 233 Copyright 2005 Altera Corporation Testbench Template Generator nGenerates HDL Testbench Template -User Inserts Test Stimulus 234 Copyright 2005 Altera Corporation Before Functional Simulation nPerform Generate Functional Simulation Netlist (Processing Menu) -Creates Pre-Synthesis Netlist -Fails Simulation if Not Performed 235 Copyright 2005 Altera Corporation Starting Simulation nProcessing Menu Start Simulation nScripting 236 Copyright 2005 Altera Corporation Simulator Report nDisplays Simulation Result Waveform View Simulation Waveform Result Waveform 237 Copyright 2005 Altera Corporation Comparing Waveforms nSelect Compare to Waveforms (View Menu) -Simulation Waveform Must Be Open nSelect VWF Comparison File 238 Copyright 2005 Altera Corporation nOriginal Waveforms (Ctrl+1) nCompared File Waveforms (Ctrl+2) nBoth Sets of Waveforms (Ctrl+3) Compared Waveforms (Simulator Report) 239 Copyright 2005 Altera Corporation Breakpoints nInterrupts Simulation at Specified Points nConsists of 2 Parts -Equation (Condition) -Action lStop lGive Error lGive Warning lGive Info Processing Simulation Debug Breakpoints Click on condition to Build Equation 240 Copyright 2005 Altera Corporation Breakpoint Conditions n -Single Condition -Ex. ena = 1 nTime = -Single Condition -time = 500ns n -Complex Tests -ena = 1 & time 500ns 241 Copyright 2005 Altera Corporation Breakpoint Equations (cont.) nNode -Opens Node Finder nOperator1 -, = nOperator2 -& (AND) -| (OR) 242 Copyright 2005 Altera Corporation Example Breakpoint Name Breakpoint Enable/Disable Breakpoints Arrange Order of Breakpoints 243 Copyright 2005 Altera Corporation nMentor Graphics - ModelSim nCadence - VERILOG-XL - NC-Verilog - NC-VHDL Using 3rd Party Simulators Synopsys VCS VSS Scirocco 244 Copyright 2005 Altera Corporation Specify Simulator nSelect EDA Tools Settings -Assignments Menu Select Simulation Tool Generate Power Input File 245 Copyright 2005 Altera Corporation Generating 3rd-Party Netlists nFull Compilation nExecute Process Individually -Processing Menu Start Start EDA Netlist Writer -Generates Files without Full Compilation nScripting 246 Copyright 2005 Altera Corporation 3rd Party Simulation Files nFunctional Simulation -Use 220models & altera_mf Megafunction Model Files nVHDL Timing Simulation -Use Quartus II-Generated VHO & SDO Files -Use _ATOMS.VHD & _ATOMS_COMPONENTS.VHD Files lLocated in edasim_lib Directory nVerilog Timing Simulation -Use Quartus II-Generated VO & SDO Files -Use _ATOMS.VO File lLocated in edasim_lib Directory 247 Copyright 2005 Altera Corporation Please go to Exercise 6 in the Exercise Manual 248 Copyright 2005 Altera Corporation nPrepared for Simulation nCreated VWF File nPerformed Functional Simulation nViewed Simulation Results Simulation Exercise Summary 249 Copyright 2005 Altera Corporation Simulation Summary nFunctional & Timing Simulation nCreating a Vector Waveform File 250 Copyright 2005 Altera Corporation Designing with Quartus II Programming/Configuration Copyright 2005 Altera Corporation Programming/Configuration nSetting Device Options nAssembler Module nProgrammer & Chain Description File -Programming Directly with Quartus II nFile Conversion -Creating Multi-Device Programming Files 252 Copyright 2005 Altera Corporation Device Options Control Configuration & Initialization of Device Setting Device Options nAssignments Device Device & Pin Options 253 Copyright 2005 Altera Corporation nDevice Options Not Dependent on Configuration Scheme -Enable Device- Wide Clear -Enable Device- Wide Output Enable -Enable Initialization Done Output Pin General Tab 254 Copyright 2005 Altera Corporation Configuration Tab nChoose Device Configuration Mode & Available Options -Generates Correct Configuration & Programming Files Every Compilation nEnables Special Features of Configuration Devices -Enable Programming File Compression -Set Configuration Clock Frequency 255 Copyright 2005 Altera Corporation Programming Files Tab nOutput Files Always Created -POF (Programming Object File) -SOF (SRAM Object File) nOther Selectable Output Files -JAM (JEDEC STAPL) -JBC (JAM Byte- Code) -RBF (Raw Binary File) -HEXOUT (Intel Hex Format) 256 Copyright 2005 Altera Corporation Other Device & Pin Option Tabs nDual-Purpose Pins -Selects Usage of Dual-Purpose Pins after Configuration Is Complete nUnused Pins -Indicates State of All Unused I/O Pins after Configuration Is Complete nError Detection CRC -Enables Internal CRC Circuitry & Frequency 257 Copyright 2005 Altera Corporation Quartus II Assembler Module nGenerates All Configuration/Programming Files -As Selected in Device & Pin Options Dialog Box nWays to Run Assembler -Full Compilation -Execute Assembler Individually lProcessing Menu Start Start Assembler lGenerates Files without Full Compilation -Switching Configuration Devices -Enabling/Disabling Configuration Device Feature -Scripting 258 Copyright 2005 Altera Corporation Open ProgrammerOpen Programmer nEnables Device Programming -ByteBlaster II or ByteBlasterMV Cables -USB-Blaster -MasterBlaster Cable -APU (Altera Programming Unit) nOpens Chain Description File (.CDF) -Stores Device Programming Chain Information 259 Copyright 2005 Altera Corporation CDF File When Adding Files, the Device for that File is Automatically Chosen nLists Devices & Files for Programming or Configuration nPrograms/Configures in Top-to-Bottom Order 260 Copyright 2005 Altera Corporation Example CDF Files Single Device Chain Multiple Device Chain 261 Copyright 2005 Altera Corporation Programmer Toolbar nStart Programming nAuto Detect Devices in JTAG Chain nAdd/Remove/Change Devices in Chain nAdd/Remove/Changes Files in Chain nChange Order of Files in Chain nSetup Programming Hardware Note: All Options are available the Edit Menu except Start Programming & Auto Detect which are available in the Processing Menu 262 Copyright 2005 Altera Corporation Setting up Programming Hardware Click on the Hardware Setup Button Choose the Hardware Settings 263 Copyright 2005 Altera Corporation Chain Programming Modes nJTAG -JTAG Chain Consisting of Altera & Non-Altera Devices nPassive Serial -Altera FPGAs Only nActive Serial -Altera Serial Configuration Devices nIn-Socket Programming -CPLDs & Configuration Devices in APU 264 Copyright 2005 Altera Corporation Programming Options To Program, Verify, Blank- Check, Examine, or Erase a Device, Check the Appropriate Boxes nProgram/Configure -Applies to All Devices nVerify, Blank-Check, Examine & Erase -Configuration Devices -MAX II, MAX 7000 & MAX 3000 nSecurity Bit & ISP Clamp -MAX II, MAX 7000 & MAX 3000 265 Copyright 2005 Altera Corporation Method 1 : Add Programming File & Leave Program/Configure Box Unchecked Bypassing Devices in JTAG Chain (1) 266 Copyright 2005 Altera Corporation Method 2 : Click on Add Device Button & Select Device to Leave the Programming File Field Blank Bypassing Devices in JTAG Chain (2) 267 Copyright 2005 Altera Corporation Click New & Create User-Defined Devices to Add Non-Altera Devices to Chain Adding Non-Altera Device to Chain 268 Copyright 2005 Altera Corporation Starting the Programmer Progress Field Shows the Percentage of Completion for the Programmer Click Program Button Once CDF File & Hardware Setup Are Complete 269 Copyright 2005 Altera Corporation Converting SOF Programming Files Creates Multi-Device .POF for Enhanced Configuration Devices Enables Compression & Other Configuration Device Options 270 Copyright 2005 Altera Corporation Please go to Exercise 7 or 8 in the Exercise Manual 271 Copyright 2005 Altera Corporation nSet Up CDF File nProgrammed FPGA Programming Exercise Summary 272 Copyright 2005 Altera Corporation Programming/Configuration Summary nSetting Device Options nGenerating Programming Files nProgramming Device or Devices in Chain nConverting Programming Files 273 Copyright 2005 Altera Corporation nDesig