VHDL复杂电路描述方法.pptx

第六讲 复杂电路的描述方法 ECE 545 Introduction to VHDL VHDL for Specification VHDL for Simulation VHDL for Synthesis ECE 545 Introduction to VHDL Levels of design description Algorithmic level Register Transfer Level Logic (gate) level Circuit (transistor) level Physical (layout) level Level of description most suitable for synthesis ECE 545 Introduction to VHDL Register Transfer Logic (RTL) Design Description Combinational Logic Combinational Logic Registers Todays Topic ECE 545 Introduction to VHDL VHDL Design Styles Components and interconnects structural VHDL Design Styles dataflow Concurrent statements behavioral Registers State machines Test benches Sequential statements Subset most suitable for synthesis VHDL的执行语句 描述结构体中电路硬件的变化特点； 结构体中的任何执行语句都是并行语句； 并行语句的种类有： 赋值类语句：数据流描述 (逻辑函数的运算) 元件类语句：结构描述 （逻辑符号的连接） 进程语句：行为描述 （电路功能的流程） ECE 545 Introduction to VHDL XOR3 Example ECE 545 Introduction to VHDL Entity (XOR3 Gate) entity XOR3 is port( A : in STD_LOGIC; B : in STD_LOGIC; C : in STD_LOGIC; RESULT : out STD_LOGIC ); end XOR3; ECE 545 Introduction to VHDL Dataflow Architecture (XOR3 Gate) architecture XOR3_DATAFLOW of XOR3 is signal U1_OUT: STD_LOGIC; begin U1_OUT A, I2 = B, Y = U1_OUT); U2: XOR2 port map (I1 = U1_OUT, I2 = C, Y = RESULT); end XOR3_STRUCTURAL; A B C RESULTXOR3 ECE 545 Introduction to VHDL Behavioral Architecture (XOR Gate) architecture XOR3_BEHAVIORAL of XOR3 is begin XOR3_BEHAVE: process (A,B,C) begin if (A xor B xor C) = 1) then RESULT = not = /= = and or nand nor xor xnor Highest Lowest ECE 545 Introduction to VHDL compare a = bc Incorrect when a = b and c else equivalent to when (a = b) and c else Correct when a = (b and c) else Priority of logic and relational operators ECE 545 Introduction to VHDL Data-flow VHDL concurrent signal assignment () conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements ECE 545 Introduction to VHDL Data Flow Instructions (2) with choice_expression select target_signal B 01 if A 16) port map(A = P1, B = P2, CMP_IN = SIG_IN, CMP_OUT = SIG_OUT ); N-bit Comparator Instantiation ECE 545 Introduction to VHDL Behavioral Design Style ECE 545 Introduction to VHDL Behavioral VHDL (subset) process statement (process) sequential signal assignment () Major instructions Sequential statements General Registers, counters, shift registers, etc. if-then-else statement State machines case-when statement Testbenches loops (for-loop, while-loop) ECE 545 Introduction to VHDL Anatomy of a Process label: process (sensitivity list) declaration part begin statement part end process; OPTIONAL ECE 545 Introduction to VHDL A process can be given a unique name using an optional LABEL This is followed by the keyword PROCESS The keyword BEGIN is used to indicate the start of the process All statements within the process are executed SEQUENTIALLY. Hence, order of statements is important. A process must end with the keywords END PROCESS. TESTING: process begin TEST_VECTOR 0) ; ELSIF ClockEVENT AND Clock = 1 THEN Q statements when choice_2 = statements when choice_n = statements end case; ECE 545 Introduction to VHDL FSM_transitions: PROCESS ( Resetn, Clock ) BEGIN IF Resetn = 0 THEN y IF s = 0 THEN y IF z = 0 THEN y IF s = 1 THEN y 2; wait for 10 ns; end loop; end loop; end process; Exit Statement - Example LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF3 IS PORT(CLK,D1:IN STD_LOGIC; Q1:OUT STD_LOGIC); END; ARCHITECTURE bhv OF DFF3 IS SIGNAL A,B:STD_LOGIC; BEGIN PROCESS(CLK) BEGIN IF CLKEVENT AND CLK =1 THEN A null; when 1|H = result := result+1; when others = null; end case; end loop; return result; end conv_integer; 数据类型转换函数的实例 程序中的一些语法解释： xrange 属性描述：返回由x的位数所指定的数据范围 ； a|b ： 将两个（或多个）信号（变量）并列的表达形 式； = : case语句的表达形式，当出现左边值时，执行右 边的语句；注意与“大于等于”区分； null：关键词语句，表示不执行任何操作； 用单引号所括的字母H、L等必须大写； 数据运算函数的实例 整数与逻辑位的加法； function “+“ (a:integer,b:bit) return integer is begin if (b = 1) then return a+1; else return a; end if; end “+“; 数据运算函数的实例 在VHDL程序中，当遇上相关情况时，程序就可 以自动调用该函数： signal a,b:integer range 0 to 15; signal c:bit; b = 3+a+c; 第1个+进行预定义的算术操作，第2个+进行函 数操作； 数据类型运算函数的实例 在VHDL程序中，当遇上相关情况时，程序就可 以自动调用该函数： signal a,b:integer range 0 to 15; signal c:bit; b = 3+a+c; 第1个+进行预定义的算术操作，第2个+进行自 定义函数操作；这称为运算重载overload。 VHDL中的结构设计：procedure 语句 过程是VHDL的一种子结构，可以看作简单的元 件。过程可以对应于一个多输入多输出的电路 模块。过程可以在结构体中调用（并行调用） ，也可以在子结构中调用。 VHDL中的过程：procedure 过程的定义： procedure 过程名（ 参量：模式 类型）is 各种说明定义； begin 执行语句（顺序语句）； End 过程名； 过程的调用： 过程名（信号列表）； procedure 语句的应用实例 architecture str of butnot1 is procedure kinv1(a: in std_logic; f: out std_logic) is begin f := not a; end kinv1; procedure kand21(a,b: in std_logic; f: out std_logic) is begin f:= a and b; end kand21; procedure 语句的应用实例 begin process(x,y) variable z1,temp:std_logic; begin kinv1(y,temp); kand21 (x,temp,z1); z=z1; end process; end str; procedure 语句的设计要点 1 过程依靠参量与主程序交换信息，参量说 明紧跟在过程名后面的括号中； 2 参量模式为：in 输入，作为常量； out