《数字逻辑设计》期末考试试题及参考解答.pdf

学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 1 页 共 9 页 电子科技大学电子科技大学 2013 -2014 学年第学年第 二二 学期期学期期 末末 考试考试 A 卷卷 课程名称：_数字逻辑设计及应用_ 考试形式： 闭卷 考试日期： 20 14 年 07 月 10 日 考试时长：_120_分钟 课程成绩构成：平时 30 %， 期中 30 %， 实验 0 %， 期末 40 % 本试卷试题由_六_部分构成，共_8_页。 题号 一 二 三 四 五 六 七 八 九 十 合计 得分 I. Fill out your answers in the blanks (3 X 10=30) 1. A circuit with 10 flip-flops can store ( 10 ) bit binary numbers, that is, include ( 1024 或 210 ) states at most. 2. A 5-bit linear feedback shift-register (LFSR) counter with no self-correction can have ( 31 或 25-1 ) normal states. 3. A modulo-24 counter circuit needs ( 5 ) D filp-flops at least. A modulo-500 counter circuit needs ( 3 ) 4-bit counters of 74x163 at least. 4. If an 74x148 priority encoder has its 1, 3, 4, and 5 inputs at the active level, the active LOW binary output is ( 010 ) . 5. State/output table for a sequential circuit is shown as Table 1. X is input and Zn is output. Assume that the initial state is S0, if the input sequence is X = 01110101, the output sequence should be ( 11001100 或 110011000 ). 【可以确定的输出序列应该有可以确定的输出序列应该有 9 位位】 . 6. Transition/output table for a sequential circuit is shown in Table 2, X is input and Y is output, the sequential circuit is a modulus ( 3 ) up/down counter. Table 1 State/output table X Sn 0 1 S0 S1 S2 S3 S0/1 S1/0 S2/0 S2/0 S1/1 S2/0 S0/0 S0/0 Sn+1/Zn Table 2 Transition/output table X Q2Q1 0 1 00 01 10 11 10/1 00/0 01/0 10/0 01/0 10/0 00/1 00/0 Q2*Q1*/Y 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 2 页 共 9 页 7. A serial sequence generator by feedback shift registers 74x194 is shown in Figure 1, assume the initial state is Q2Q1Q0 = 100, the feedback function LIN = Q2Q1 + Q2Q0, the output sequence in Q2 is ( 100110 循环输 出 ). Figure 1 8. When the input is 01100000 of an 8 bit DAC, the corresponding output voltage is 3.76V. The output voltage range for the DAC is ( 0 9.99 或 56 8 22 12 76. 3 + 或 96 255 76. 3 )V. 【本题并未对误差范围进行要求， 一般可保留 本题并未对误差范围进行要求， 一般可保留 2 位小数。由于考试时没有计算器，写出算式也可位小数。由于考试时没有计算器，写出算式也可】 II. Please select the only one correct answer in the following questions.(2 X 5=10) 1. The output signal of ( A ) circuit is 1-out-of-M code. A. binary decoder B. binary encoder C. seven-segment decoder D. decade counter 2. An asynchronous counter differs from a synchronous in ( B ). A. the number of states in its sequence B. the method of clocking C. the type of flip-flop used D. the value of the modulus 3. There are ( D ) unused states for an n-bit Jonson counter. A. n B. 2n C. 2n-n D. 2n-2n 4. The capacity of a memory that has 12 bits address bus and can store 8 bits at each address is ( A ). A. 32768 B. 8192 C. 20 D. 256 5. Consider the following 44 “two-dimensional arbiter” shown in Figure 2 with inputs R0,0,R0,1,R0,2,R0,3, R1,0,R1,1,R1,2,R1,3, R3,0,R3,1,R3,2,R3,3 (“requests”) and outputs G0,0,G0,1,G0,2,G0,3, G1,0,G1,1,G1,2,G1,3, G3,0,G3,1,G3,2,G3,3 (“grants”). Wi,0s and N0,j s are also inputs, and Ei,4s and 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 3 页 共 9 页 S4,j s are also outputs. Assume 1ns gate delay for all gates (i.e., 2-AND and INV). The longest delay in Fig. 2 (in ns) is ( B ). A. 19 B. 21 C. 23 D. 25 Figure 2. 4 4 two-dimensional arbiter. Figure 3. Logic for rectangle box. 【提示：不要被上图的气势所吓倒。从提示：不要被上图的气势所吓倒。从 Figure 3 可知，每个小方盒的最大延迟是可知，每个小方盒的最大延迟是 3 个门，即个门，即 3ns； 从从 Figure 2 可知， 最长通路经过了可知， 最长通路经过了 7 个小方盒， 如图中蓝线所示， 因此， 此电路最大延迟为个小方盒， 如图中蓝线所示， 因此， 此电路最大延迟为 37 = 21ns 】 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 4 页 共 9 页 III. Analyze the clocked synchronous state machine shown in Figure 4. (15) (1) Write out the excitation equations, the state transition equations and the output equations of the circuit. (4) (2) Fill out the transition/output table (6) (3) Assume initial state is 000, draw the state transition /output diagram. Important: Only include reachable states in the diagram (3) (4) With initial state = 000, what states, if any, are not reacheable? Please list the unreachable states. (2) D-FF D-FF D-FF D2 AND AND OR ANDD1 D0 Q1 Q0 I CP F Q2 Figure 4 参考答案：参考答案： (1) The excitation equation : D0 = D1 = IQ0 + IQ0, D2 = IQ0 The state equation : Q0* = Q1* = D0 = D1 = IQ0 + IQ0, Q2* = D2 = IQ0 The output equation : F = Q2Q1Q0， (2) The transition /output table: I Q2Q1Q0 Q2*Q1*Q0* F 0 000 000 0 0 001 111 0 0 010 000 0 0 011 111 0 0 100 000 0 0 101 111 0 0 110 000 0 0 111 111 1 1 000 011 0 1 001 000 0 1 010 011 0 1 011 000 0 1 100 011 0 1 101 000 0 1 110 011 0 1 111 000 1 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 5 页 共 9 页 Transition/output table I Q2Q1Q0 0 1 000 100, 0 010, d 011 000, 1 100, 1 100 010, 1 100, 0 010 010, d 011, 1 Q2*Q1*Q0*, F (3) The sate transition /output diagram: (4) With initial state = 000, the unreachable states are: 001, 010, 100, 101, 110 IV. Consider the following Mealy machine with initial state A. (“d” means dont care.) (15) Q2*Q1*Q0* F Q2Q1Q0 I = 0 I = 1 I = 0 I = 1 A B C D C A D D D C C B 0 1 1 d d 1 0 1 Assume the following state encoding: StateQ2Q1Q0 A 000 B 011 C 100 D 010 (1) Please fill out the transition/output table . (8) 参考答案：参考答案： (2) Fill-in K-Map of D2,D1,D0, and output F if realized with D flip-flops. (3) 参考答案：参考答案： 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 6 页 共 9 页 D2 00011110 00 01 11 10 1 d 1 d 1 d d d d d d Q1Q0 I Q2 D0 00011110 00 01 11 10 d 1 dd dd dd d Q1Q0 I Q2 (3) Derive the minimum two-level logic for D2, D1, D0 and F. (4) 参考答案：参考答案： D2 = IQ2Q1 + IQ2 + IQ0 或 D2 = (I+Q2+Q0) (I+Q2) (I+Q1) D1 = IQ2Q1 + IQ2 + Q1Q0 或 D1 = IQ2Q0 + IQ2 + Q1Q0 或 D1 = Q0(I+Q2)(I+Q2+Q1) D0 = IQ1Q0 F = IQ2 + Q1 或 F = (Q2+Q1) (I+Q2) 或 F = (Q2+Q1) (I+Q1) V. Consider the following sequential logic diagram in Figure 5. Assume the gate delay is 1 ns for 2-AND and 2ns for 2-XOR. Assume the positive edge-trigged flip-flop delay is TdelayFF = 1 ns, and Assume the positive edge-trigged flip-flop setup time is also TsetupFF = 1 ns. Fill out the rest of the timing diagram for B, C, D, and Q. (15) 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 7 页 共 9 页 Figure 5 参考答案：参考答案： Figure 4 VI. 74X163 is a synchronous 4-bit binary counter with synchronous load and synchronous clear inputs, the basic function table is shown as follow. Design a modulo-13 counter, using one 74X163 and some necessary gates, with the following counting sequence: 1, 2, 3, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 1, 2, . (15) (1) Fill in the following K-Maps of LD_L, D, C, B, A with minimum cost. (6) (2) Derive the minimum two-level logic expressions for LD_L, D, C, B, A. (6) (3) Draw the logic diagram of this counter. (3) 得 分 学院 姓名 学号 任课老师 考场教室_选课号/座位号 密封线以内答题无效 第 8 页 共 9