嵌入式系统架构软体设计.ppt

嵌入式系统架构软体设计 q嵌入式系统架构软体设计 -using ARM q qDay #3,#4,#5 Modules Outline q q 嵌入式系统架构软体设计 -using ARM 课程介绍 q Day #3 Simple RISC Assembly Language ARM Assembly Language ARM Development Suite 使用练习 q Day #4 Arm Instruction set Important ASM Programming Skills ARM/THUMB/C Interworking q Day #5 ARM Exception Handler Build ARM ROM Image Use NET-Start! ucLinux BSP 嵌入式系统架构软体设计 -using ARM 嵌入式系统产品设计流程概观 嵌入式系统架构软体设计 -using ARM q ARM system-on-chip Architecture, 2nd ed. q ARM architecture reference manual, 2nd ed. q ARM Development Suite-Getting Started q ARM Development Suite-Developer Guide q ARM Development Suite-Assembler Guide q / q 2002嵌入式系统开发经验 q Building powerful platform with Windows CE q Software Engineering, A practitioners Approach 3rd ed. q Professional Symbian Programming 嵌入式系统架构软体设计 -using ARM 嵌入式系统架构软体设计 -using ARM Module #3-1: Simple RISC Assembly Concept 嵌入式系统架构软体设计 -using ARM RISC精简指令集vs.CISC复杂指令集 Hardware instruction decode logic Pipeline execution Single execution Large microcode ROMs to decode instruction Allow little pipeline Many cycles to completer a single instruction A smaller die size A shorter development time A higher performance Poor code density 嵌入式系统架构软体设计 -using ARM MUO 一个简单的处理器 嵌入式系统架构软体设计 -using ARM MUO指令集与资料路径 指令Opcode功能 LDA S0000ACC=memS STO S0001memS=ACC ADD S0010ACC=ACC+memS SUB S0011ACC=ACC-memS JMP S0100PC=S JGE S0101If ACC= PC=S JNE S0110If ACC!=0 PC=S STP 0111stop 指令规则 嵌入式系统架构软体设计 -using ARM 指令执行范例 qADD 0x16A ACC:=ACC+mem0x16A 嵌入式系统架构软体设计 -using ARM 运算范例 C function: Main() C=A+B; MUO 机器指令 LDA 0x100 ADD 0x104 STO 0x108 指令Opcode功能 LDA S0000ACC=memS STO S0001memS=ACC ADD S0010ACC=ACC+memS SUB S0011ACC=ACC-memS JMP S0100PC=S JGE S0101If ACC= PC=S JNE S0110If ACC!=0 PC=S STP 0111stop 嵌入式系统架构软体设计 -using ARM 练习： MUO微处理器的运算 0x100 LDA 0x100 0x002 SUB 0x104 0x004 STO 0x100 0x006 JNE 0x000 0x008 STP 请描述此段程式的动作，暂存器值的变化 、与资料流。请用C语言来写出这段程式 码。 指令Opcode功能 LDA S0000ACC=memS STO S0001memS=ACC ADD S0010ACC=ACC+memS SUB S0011ACC=ACC-memS JMP S0100PC=S JGE S0101If ACC= PC=S JNE S0110If ACC!=0 PC=S STP 0111stop 嵌入式系统架构软体设计 -using ARM 嵌入式系统架构软体设计 -using ARM Module #3-2: ARM Assembly Language 嵌入式系统架构软体设计 -using ARM ARM7TDMI资料流 e.g.r3:=r4+(r4,2) ADD r3,r4,r4,LSL#2 A bus B bus 嵌入式系统架构软体设计 -using ARM ARM 的暂存器 q 30 general-purpose, 32 bits registers q 1 Program Counter (PC) q 1 Current Program Status Register (CPSR) q 5 Saved Program Status Registers (SPSR) User mode FIQ mode irq mode SVC mode abort mode undefined mode 嵌入式系统架构软体设计 -using ARM Program Status Register q CPSR: Currrent Program Status Regiter q SPSR: Saved Program Status Register q Condition code flags -N: Negative rsult from ALU - Z: Zero result from ALU - C: ALU operation Carried out - V: ALU operation overflowed q Inerrupt Disable bits - I: disable the IRQ - F: Disable the FIQ q T bit - Architechture xT only - T=0: ARM state - T=1: Thumb state q Q: Stickly Overflow flag - Architecture 5TE only - QADD, QSUB qJ: Processor in Jazelle state Architecture 5TEJ only qMode bits Specify the processor mode 10000 User 10001 FIQ 10010 IRQ 10011 SVC 10111 Abort 11011 Undef 11111 System 31 30 29 28 27 24 7 6 5 4 0 N Z C V Q J undefined I F T mode 嵌入式系统架构软体设计 -using ARM Program counter R15 q ARM state: All ARM instructions are four bytes long (one 32-bit word) and are always aligned on a word boundary. The PC value is stored in bits 31:2 with bits 1:0 undefined. q In Thumb state: All instructions are 16 bits wide, and halfword aligned The PC value is stored in bits31:1 with bits 0 undefined. q In Jazelle state: All instructions are 8 bits wide. The processor performs a word access to read 4 instructions at once. 嵌入式系统架构软体设计 -using ARM Link Register R14 q Register 14 is the Link Register (LR). q This register holds the address of the next instruction after a Branch and Link (BL) instruction, which is the instruction used to make a subroutine call. q At all other times, R14 can be used as a general-purpose register 嵌入式系统架构软体设计 -using ARM Other Register R0-R13 q The remaining 15 registers have no special hardware purpose. q Their uses are defined purely by software. q By convention, ARM assembly language use R13 as Stack Pointer. q C and C+ compilers always use R14 as the Stack Pointer(SP) 嵌入式系统架构软体设计 -using ARM Structure of ARM Assembly Language Module AREA Sectionname,attr,attr Start of New code or data section. CODE: contain machine instructions. READONLY: section should not be written to. Other attr: DATA, NOINIT, READWRITE, Declares an entry point to a program. Labels. Declares the end of the source file. 嵌入式系统架构软体设计 -using ARM Calling Subroutines Uses BL q BL destination destination is the label on the first instruction of the subroutine. BL does: place the return address in the link register (R14) sets PC to the address of the subroutine. In the subroutine we can use “MOV pc,lr” to return. By convention, R0-R3 are used to pass parameters. 嵌入式系统架构软体设计 -using ARM Calling Subroutines Example ; name this block of code ; mark first instruction ; to execute ; Set up parameters ; Call subroutine ; angel_SWI reason_report Exception ; ADP_Stopped_ApplicationExit ; ARM semihosting SWI ; Subroutine code ; Return from subroutine. ; Mark end of file 嵌入式系统架构软体设计 -using ARM Constant Data Types q Numbers Numeric constants are accepted in three forms: Decimal, for example, 123 Hexadecimal, for example, 0x7B n_XXX where: n is as base between 2 and 9 xxx is a number in that base. q Boolean TRUE and FALSE must be written as TRUE and FALSE. q Characters constants consist of opening and closing single quotes X, enclosing either a single character or an escaped character, using the standard C escape characters. q Strings consist of opening and closing double quotes “XXXX”. If double quotes or dollar signs are used within a string as literal text characters, they must be represented by a pair of the appropriate character. For example, you must use $ if you require a single $ in the string. The standard C escape sequences can be used within string constants. 嵌入式系统架构软体设计 -using ARM q Almost all ARM instructions can be conditionally executed. e.g. ADDS r0,r1,r2 ADDEQ r0,r1,r2 q Execute if the N,Z,C and V flags in the CPSR satisfy a condition specified in the instruction, otherwise, NOP. Conditional ARM Instructions 嵌入式系统架构软体设计 -using ARM q Almost every ARM instruction can be executed conditionally on the state of the ALU state flags in the CPSR. q Add an S suffix to an ARM data processing instruction to make it update the ALU state flags in the CPSR E.g. ADDS r0,r1,r2; r0=r1+r2 and update ALU status in CPSR. q In ARM state, you can: update the ALU status flags in the PSR on the result of a data operation execute several other data operation without updating the flags execute following instructions or not, according to the state of the flags updated in the first operation. q In Thumb state most data operations always update the flags and conditional execution can only be achieved using the conditional branch instruction (B). q Do not use the S suffix with CMP, CMN, TST, or TEQ. These comparison instructions always update the flag Conditional Execution 嵌入式系统架构软体设计 -using ARM ALU Status Register in CPSR q N Set when the result of the operation was Negative. q Z Set when the result of the operation was Zero. q C when the result of the operation was Carry. A carry occurs if the result of an addition is greater than or equal to 232 If the result of a instruction is positive, or as the result of an inline barrel shifter operation in a move or logical instruction. q V Set when the operation caused oVerflow. Overflow occurs if the result of an add, subtract, or compare is greater than or equal to 231, or less than 231. q Q ARM architecture v5Eonly. Sticky flag. Used to detect saturation in special saturating arithmetic instructions (e.g. QAD, ASUB, QDADD, and QDSUB), Or overflow in certain multiply instructions (SMLAxy and SMLAWy) 嵌入式系统架构软体设计 -using ARM Conditional Code Suffixes 嵌入式系统架构软体设计 -using ARM Conditional Code Examples q ADD r0,r1,r2;r0=r1+r2, dont update flags q ADDS r0,r1,r2;r0=r1+r2, and update flags q ADDCSS r0,r1,r2;if C flag set then r0=r1+r2, and update flags q CMP r0,r1;update flags based on r0-r1. q Example code sequence: MOV R0,#0 LOOP ADD R0, R0, #1 CMP R0, #10 BNE LOOP SUB R1, R1,R0 嵌入式系统架构软体设计 -using ARM Write Efficient and small size Code by Conditional Instruction 嵌入式系统架构软体设计 -using ARM Exercise Write program by ARM assembly, else r2=r2-r1; 嵌入式系统架构软体设计 -using ARM 嵌入式系统架构软体设计 -using ARM Module #3-3: ARM Development Suite使用练习 嵌入式系统架构软体设计 -using ARM ARM ADS 1.2 Others: C r0:=r1+r2 q 大部分的指令，可以在一个周期内执行完成 q 指令皆可为有条件式执行 q Load/store 架构. 嵌入式系统架构软体设计 -using ARM Thumb 指令集 q Thumb指令长度为16 bits 针对程式码的密度最佳化， 约为65%的ARM code size 适合小记忆体系统 Thumb指令支援的功能为ARM指令集的一部分 执行期间必须切换到Thumb模式 ADDSr1,r1,#3 ADDr1,#3 嵌入式系统架构软体设计 -using ARM Jazelle q Jazelle 技术可以让ARM执行8-bit Java Bytecode 硬件可以支援到95%的bytecodes 速度约为一般软件JVM的五倍 嵌入式系统架构软体设计 -using ARM ARM 指令集分类 q Branch instructions q Data-processing instructions q Load and store instructions q Status register transfer instructions q Coprocessor instructions q Exception-generating instructions. 嵌入式系统架构软体设计 -using ARM Branch instructions q B Branch q BL Branch with link Store the return address to r14 e.g. CMP r2, #0 BLEQ function function MOV PC, r14 嵌入式系统架构软体设计 -using ARM Branch Instruction Encoding q The range of the branch instruction is +/- 32 Mbytes q L: the branch and link variant. Assembly Format: BLSRm BLS 嵌入式系统架构软体设计 -using ARM Branch instructions example q e.g. C if (a=0) unction 1 (1); Else c Function 1() function2(); Function2() return; qASM function 1 STMFDr13!, r0-r4, r14 BL function2 LDMFDr13!, r0-r4, pc function2 MOV pc, r14 嵌入式系统架构软体设计 -using ARM Data-processing instructions Encoding Assembly Format: S Rd, Rn,# S Rd, Rn,Rm, shift 嵌入式系统架构软体设计 -using ARM Data Processing Opode Assembly Format: SRd, Rn # SRd, Rn Rm, Opcode Mnemonic MeaningEffect 24:21 0000ANDLogical bit-wise AND Rd:=Rn r0=r1+r2 SUBr0,r1,r2; r0=r1-r2 RSBr0,r1,r2; r0=r2-r1 q Bit-wise logical operations AND r0,r1,r2; r0 = r1 r0 = r1| r2 EORr0,r1,r2; r0 = r1 xor r2 BICr0,r1,r2; r0 = and not r2; bit clear 嵌入式系统架构软体设计 -using ARM Example Data-processing Instructions (cont.) q Register movement operations MOV r0,r2; r0=r2 MVN r0,r2; r0=not r2 q Comparison operations (set condition code bits N, Z, C, V) CMP r1,r2; set cc on r1-r2 q Immediate operands ADD r3,r3,#1 ; r3=r3+1 ANDr8,r7, # r8=r77:0 r3:= r2+8*r1 e.g. #2 r0=r1*5 r0=r1+(r1*4) ADD r0 ,r1, r1, LSL #2 嵌入式系统架构软体设计 -using ARM Multiply instruction binary encoding Assembly Format MULS Rd, Rm, Rs MLAS Rd, Rm, Rs, Rn S RdHi, RdLo, Rm, Rs RdHi: the most significant 32 bits of 64-bit format number RdLo: the least significant 32 bits of 64-bit format number Opcode Mnemonic Meaning Effect 23:21 000 MUL Multiply (32-bit result)Rd:=(Rm*Rs)31:0 001 MLA Multiply-accumulate (32-bit result)Rd:=(Rm*Rs+Rn)31:0 100 UMULL Unsigned multiply longRdHi:RdLo:=Rm*Rs 101 UMLAL Unsigned multiply-accumulate longRdHi:RdLo+=Rm*Rs 110 SMULL Signed multiply longRdHi:RdLo:=Rm*Rs 111 SMLAL Signed multiply-accumulate longRdHi:RdLo+=Rm*Rs 嵌入式系统架构软体设计 -using ARM Assembly Format: CLZS Rd, Rm q Sets Rd to the number of the bit position of hr most significant 1 in Rm. If Rm=0 Rd=32. q E.g. MOV r0, # y=mul_ten(x); int mul_ten(x) return 10*x; 嵌入式系统架构软体设计 -using ARM Single Word and Unsigned Byte Data Transfer Instruction Binary Encoding Assemble Format: LDR|STRB Rd,Rn, !; Pre-indexed form LDR|STRB Rd,Rn, ; Post-indexed form LDR|STRB Rd,LABEL; PC-relative form 嵌入式系统架构软体设计 -using ARM Load and Store Examples q Single register and store LDRr0,r1 ;r0:=mem32r1 STR r0r1; mem32r1:=r0 q Base plus offset addressing Pre-indexing LDR r0,r1, #4 ;r0:=mem32r1+4 Auto indexing LDR r0,r1, #4! ;r0:=mem32r1+4, r1=r1+4 Post-indexed LDR r0,r1, #4 ;r0:=mem32r1, r1=r1+4 PC-relative LDR r1, UART_ADD ; UART address into r1 STRBr0,r1; store data to UART UART_ADD address literal 嵌入式系统架构软体设计 -using ARM Half-word and Signed Byte Data Transfer Instruction Binary Encoding Assemble Format: LDR|STRH |SH|SB Rd;Rn, ! ; Pre-indexed form LDR|STRH |SH|SB Rd;Rn, ; Post-indexed form An unsigned value is zero- extended to 32 bits when loaded; A singed value is extended to 32 bits by replicating the most significant bit of the data. 嵌入式系统架构软体设计 -using ARM Half-word Load/Store Example ADR r1,ARRAY1; half-word array start ADR r2,ARRAY2; word array start ADR r3,ENDARR1; ARRAY1 end +2 LOOP LDRSH r0,r1,#2; get signed half-word STR r0,r2,#4; save word CMP r1,r3; check for end of array BLT LOOP; if not finished, loop 嵌入式系统架构软体设计 -using ARM 练习：字串复制 q 写一个Assembly程序做字串复制的动作 q 用ADS环境 A=“Hello, this is a sunny day!” B=“ “ 嵌入式系统架构软体设计 -using ARM Multiple Register Data Transfer Instruction Binary Encoding In a non-user mode, CPSP may be restored by: LDM|Rn!, Full or empty: The stack pointer can either point to the last item in the stack (a full stack), or the next free space on the stack (an empty stack). Assembly Format: LDM|STM Rn!, IA: Increment after. IB: Increment before. DA: Decrement after. DB: Decrement before 嵌入式系统架构软体设计 -using ARM Example Addressing Mode for LDM/STM 嵌入式系统架构软体设计 -using ARM ISR Example q e.g. Interrupt handler _irq void IRQHandler(void) volatile unsigned int *base=(unsigned int *) 0x80000000; If (*base=1) C_int_handler_1( ); *(base+1)=( ); IRQHandler PROC STMFDspl,ro-r4,r12,lr MOVr4,#0x80000000 LDRr0, r4,#0 SUBsp,sp,#4 CMPr0,#1 BLEQ C_int_handler MOV r0,#0 STR r0,r4,#4 ADD sp,sp,#4 LDMFD spl,r0-r4,r12,lr SUBSpc,lr,#4 嵌入式系统架构软体设计 -using ARM Swap Memory And Register Instruction Binary Encoding Assembly Format: SWPB Rd,Rm,Rn 嵌入式系统架构软体设计 -using ARM SWP Example ADR r0,SEMAPHORE SWPB r1,r1,r0 ; exchange byte r0 r1 r? 0 嵌入式系统架构软体设计 -using ARM Status Register to General Register Transfer Instruction Binary Encoding Assembly Format: MRSRd,CPSR|SPSR E.g. MRS r0, CPSR; move the CPSR to r0 MRS r3, CPSR; move the SPSR to r3 Note: The SPSR form should not be used in user or system mode. 嵌入式系统架构软体设计 -using ARM Transfer to Status Register Instruction Binary Encoding Assembly Format: MRSCPSR_f|SPSR_f, # MRSCPSR_|SPSR_, Rm C - the control field PSR7:0 X the extension field PSR15:8 S the status field PSR23:16 F the flags field PSR31:24 嵌入式系统架构软体设计 -using ARM MSR Example q Set N,C,V,Z flages: MSRCPSR_f, # set all the flags q Set C flag, preserving N,Z, and V MRSr0,CPSR ; move the CPSR to r0 ORRr0,r0,# set bit 29 of r0 MSR CPSR_f,r0 : move back to CRSR 嵌入式系统架构软体设计 -using ARM 练习：切换ARM操作模式 q 写一段程序，将ARM由Supervisory mode切换到IRQ mode。 q 用ADS环境。 31 30 29 28 27 24 7 6 5 4 0 N Z C V Q J underfined I F T mode q Mode bits Specify the processor mode 10000User 10001 FIQ 10010 IRQ 10011 SVC 0111Abort 11011 Undef 11111 System 嵌入式系统架构软体设计 -using ARM Coprocessor Instructions q There are 3 types: Coprocessor data operations CDP:initiate a coprocessor data processing operation Coprocessor Register transfers MRC:Move to ARM register from coprocessor register MCR:Move to coprocessor register from ARM register Coprocessor Memory transfer LDC:load coprocessor register from memory STC:store from coprocessor register to memory 嵌入式系统架构软体设计 -using ARM Exception-generating R1=0x18 Can load any 8-bit constant, giving a range of 0x00 to 0xFF q MVN: load the bitwise complement of these values. The numerical values are (n+1). Compiler ERROR MSG: Immediate n out of range for this operation. 224 嵌入式系统架构软体设计 -using ARM Loading with LDR Rd,=const q The LDR Rd,=const pseudo-instruction can construct any 32-bit numeric constant in a single instruction q The LDR pseudo-instruction generates the most efficient code for a specific constant: If the constant can be constructed with a MOV or MVN instruction, the assembler generates the appropriate instruction. If the constant cannot be constructed with a MOV or MVN instruction, the assembler: Places the value in a literal pool. Generates an LDR instruction with a program-relative address that reads the constant from the literal pool. q e.g.: LDR Rn,pc,#offset to literal pool ;load register n with one word from the address pc+offset Literal Pool: A portion of memory embedded in the code to hold constant values. 嵌入式系统架构软体设计 -using ARM LDR ; c:ARMADSv1_2Examplesasmloadcon.s AREALoadcon, CODE, READONLY ENTRY START BLfunc1 BLfunc2 stop MOVr0,#0x18; =MOV R0, #42 LDRr1, =0x20026 SWI0x123456 func1 LDRr0, =42; =MOV R0, #42 LDRr1, =0x55555555; =LDR R1, PC, #offset to Literal Pool l LDRr2, =0xFFFFFFFF; =MVN R2, #0 MOVpc, lr LTORGLitetal Pool l constains Litetal 0x55555555 func2 LDRr3, =0x55555555; =LDR R3, PC, #offset to Literal Pool l LDRr4, =0x66666666; If this is uncommented it is out of reach ; fails, because Literal Pool 2 MOV pc, lr LargeTable SPACE 4200 ; Starting at the current location ; clears a 4200 bytes area of memory ; to zero, reserves a zeroed block of memory ; Literal Pool 2 is empty END 嵌入式系统架构软体设计 -using ARM Loading Addresses into Registers q Direct loading with ADR and ADRL q Loading addresses with LDR Rd, =label. 嵌入式系统架构软体设计 -using ARM Direct Loading with ADR q The assembler converts an ADR Rn, label pseudo-instruction by generating: A single ADD or SUB instruction that loads the address, if it is in range An error message