[信息与通信]vhdl考试程序总结.doc

64位计数器12计时器83. 波形94显示译码器105. 表决器117四选一148译码器149奇偶校正1610 移位寄存器1711 四位减法2012 选择器2213 循环显示135792213 转换成bcd吗2314 走马灯2415 全加器2516 8421 BCD码转换为余3码电路2717 触发器2818 编码器3264位计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;USE IEEE.STD_LOGIC_ARITH.ALL;entity mchcounter isport(clk,clr,s,en,updn:in std_logic; d:in integer range 0 to 63; m: in integer range 0 to 63;co:out std_logic;q:buffer integer range 0 to 63);end mchcounter;architecture a1 of mchcounter is-定义计数最大值mtempsignal m_temp:integer range 0 to 63;beginprocess(clk,clr,m)beginm_temp=m-1;-清零功能if clr=1 then q=0;co=0;-以时钟信号的上升沿为计数触发器条件elsif clkevent and clk=1then-置数功能if s=1 then qm_temp then q=m_temp;-计数使能控制功能elsif en=1 then if updn=1 then -计数加法if q=m_temp then q=0;co=1;else q=q+1;co=0;end if; elsif updn=0 then -计数减法 if q=0 then q=m_temp;co=1; else q=q-1;co=0;end if; end if;end if;end if;end process;end a1;-(1)clk为时钟信号，由时钟信号的上升沿触发计数；-(2)m为模值输入端，当其变化时，计数容量相应发生变化?-(3)clr为清零控制端，当其为高电平时清零?-(4)s为置数控制端，当其为高电平时将置数输入端d的数据加载到输出端q；-(5)en为使能控制端，当其为高电平时正常计数，当其为低电平时暂停计数；-(6)updn为计数方向控制端，当其为高电平时计数器加法计数，当其为低电平时计数器减法计数。LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY scount IS PORT (CLK : IN STD_LOGIC; RST : IN STD_LOGIC; ENA : IN STD_LOGIC; OUTY : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT : OUT STD_LOGIC ); END scount;ARCHITECTURE behav OF scount IS SIGNAL CQI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINP_REG: PROCESS(CLK, RST, ENA) BEGIN IF RST = 1 THEN CQI = 0000; ELSIF CLKEVENT AND CLK = 1 THEN IF ENA = 1 THEN CQI = CQI + 1; ELSE CQI = 0000; END IF; END IF; OUTY = CQI ;END PROCESS P_REG ;COUT = CQI(0) AND CQI(1) AND CQI(2) AND CQI(3); END behav;LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY yibujishu IS PORT(CLK:IN STD_LOGIC; COUNT:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END ENTITY yibujishu;ARCHITECTURE ART2 OF yibujishu IS SIGNAL COUNT_IN_BAR:STD_LOGIC_VECTOR(4 DOWNTO 0); COMPONENT D_ff IS PORT(CLK,D:IN STD_LOGIC; Q,nq:OUT STD_LOGIC); END COMPONENT; BEGIN COUNT_IN_BAR(0)COUNT_IN_BAR(I), D=COUNT_IN_BAR(I+1),Q=COUNT(I),nq=COUNT_IN_BAR(I+1); END GENERATE; END ARCHITECTURE ART2;高级计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;USE IEEE.STD_LOGIC_ARITH.ALL;entity mchcounter isport(clk,clr,s,en,updn:in std_logic; d:in integer range 0 to 63; m: in integer range 0 to 63;co:out std_logic;q:buffer integer range 0 to 63);end mchcounter;architecture a1 of mchcounter is-定义计数最大值mtempsignal m_temp:integer range 0 to 63;beginprocess(clk,clr,m)beginm_temp=m-1;-清零功能if clr=1 then q=0;co=0;-以时钟信号的上升沿为计数触发器条件elsif clkevent and clk=1then-置数功能if s=1 then qm_temp then q=m_temp;-计数使能控制功能elsif en=1 then if updn=1 then -计数加法if q=m_temp then q=0;co=1;else q=q+1;co=0;end if; elsif updn=0 then -计数减法 if q=0 then q=m_temp;co=1; else q=q-1;co=0;end if; end if;end if;end if;end process;end a1;-(1)clk为时钟信号，由时钟信号的上升沿触发计数；-(2)m为模值输入端，当其变化时，计数容量相应发生变化?-(3)clr为清零控制端，当其为高电平时清零?-(4)s为置数控制端，当其为高电平时将置数输入端d的数据加载到输出端q；-(5)en为使能控制端，当其为高电平时正常计数，当其为低电平时暂停计数；-(6)updn为计数方向控制端，当其为高电平时计数器加法计数，当其为低电平时计数器减法计数。十二位计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity count12 isport (CR,LD,CLK: in std_logic;QIN: in std_logic_vector(3 downto 0); - zhi shu QOUT: out std_logic_vector(3 downto 0); end count12;architecture one of count12 isbeginprocess(CLK)variable tma: std_logic_vector(3 downto 0);beginif CR=0 thentma:=0000;elsif CLKevent and CLK=1 thenif LD=0 then tma:=QIN;end if;if LD=1 thenif tma=1100 then tma:=0000;else tma:=tma+1;end if;end if;end if;QOUT num numnull; end case; end process p1;p2:process(ckdsp) begin if ckdspevent and ckdsp=1 then cnt8=cnt8+1; end if; if cnt8=010 then cnt8=000; end if; end process p2;end;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY COUNT10 IS PORT(CLK,R,S:IN STD_LOGIC;DATA:IN STD_LOGIC_VECTOR(3 DOWNTO 0);CO:OUT STD_LOGIC;Q:BUFFER STD_LOGIC_VECTOR(3 DOWNTO 0);END COUNT10;ARCHITECTURE test OF COUNT10 ISBEGINCO=1 WHEN (Q=1001) ELSE 0;PROCESS(CLK,R)BEGINIF (R=0) THEN Q=0000;ELSIF (CLKEVENT AND CLK=1) THENIF(S=1) THEN Q=DATA;ELSIF (Q=9) THEN Q=0000;ELSE Q=Q+1;END IF;END IF;END PROCESS;END test;2计时器 异步计数 ARCHITECTURE ART2 OF yibujishu IS SIGNAL COUNT_IN_BAR:STD_LOGIC_VECTOR(4 DOWNTO 0); COMPONENT D_ff IS PORT(CLK,D:IN STD_LOGIC; Q,nq:OUT STD_LOGIC); END COMPONENT; BEGIN COUNT_IN_BAR(0)COUNT_IN_BAR(I), D=COUNT_IN_BAR(I+1),Q=COUNT(I),nq=COUNT_IN_BAR(I+1); END GENERATE; END ARCHITECTURE ART2;3. 波形library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity aquare_gen is port(clk:in std_logic; input:in std_logic_vector(6 downto 0); q:out std_logic);end aquare_gen;architecture a of aquare_gen is signal ff:bit;beginprocess(clk)variable num:integer range 0 to 100;beginif clkevent and clk=1 then if numinput then ff=1; num:=num+1; elsif num100 then num:=num+1; ff=0; else num:=0; end if;end if;end process;process(clk)begin if clkevent and clk=1 then if ff=1 then q=1; else qSGSGSGSGSGSGSGSGSGSGSGNULL;END CASE;END PROCESS;END;七段 library ieee; use ieee.std_logic_1164.all; entity yima is port(d0,d1,d2,d3:in std_logic;a,b,c,d,e,f,g:out std_logic); end yima; architecture behav of yima is signal m: std_logic_vector(3 downto 0); signal seg7:std_logic_vector(6 downto 0); begin m=d3&d2&d1&d0;WITH m SELECTseg7=0111111 when 0000 , 0000110 when 0001 , 1011011 when 0010 , 1001111 when 0011 , 1100110 when 0100 , 1101101 when 0101 , 1111101 when 0110 , 0000111 when 0111 , 1111111 when 1000 , 1100111 when 1001 , 1110111 when 1010 , 1111100 when 1011 , 0111001 when 1100 , 1011110 when 1101 , 1111001 when 1110 , 1110001 when 1111 , 0000000 when others; g=seg7(6); f=seg7(5); e=seg7(4); d=seg7(3); c=seg7(2); b=seg7(1); a=seg7(0); end behav;5. 表决器表决器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY BIAOJUE ISPORT( CLK:IN STD_LOGIC; A,B,C,D,E:IN STD_LOGIC; COU:OUT STD_LOGIC); END; ARCHITECTURE ONE OF BIAOJUE ISSIGNAL CNT:STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL ZH:STD_LOGIC;SIGNAL ZH1:STD_LOGIC;BEGIN PROCESS(CLK,A,B,C,D,E)VARIABLE CNT_LB:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGINIF CLKEVENT AND CLK=1 THEN CNT_LB:=CNT_LB+1;IF CNT_LB10 THEN ZH1=1; -喇叭响-ELSE ZH1=0;END IF;END IF;CNT ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZH ZHZH=1;END CASE; END PROCESS ;COU num numnull; end case; end process p1;p2:process(ckdsp) begin if ckdspevent and ckdsp=1 then cnt8=cnt8+1; end if; if cnt8=010 then cnt8=000; end if; end process p2;end;7四选一LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY xzq4_1 ISPORT( a,b:IN STD_LOGIC;i0,i1,i2,i3:IN STD_LOGIC;f:OUT STD_LOGIC);END xzq4_1;ARCHITECTURE behavior OF ymq83 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0);BEGIN selFFFFNULL; END CASE;END behavior8译码器2-4译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity decode_behavior isport (A1,B1,G1:in std_logic;Y1:out std_logic_vector(3 downto 0);end entity decode_behavior;architecture behavioral of decode_behavior issignal data: std_logic_vector(1 downto 0);begindata Y1Y1Y1Y1Y1=1111;end case;else Y1=1111;end if;end process;end behavioral;3-8译码器LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ymq83 ISPORT(A,B,C:IN STD_LOGIC;Y:OUT STD_LOGIC_VECTOR(7 DOWNTO 0);END ymq83;ARCHITECTURE behavior OF ymq83 IS SIGNAL INDATA:STD_LOGIC_VECTOR(2 DOWNTO 0);BEGIN INDATA Y Y Y Y Y Y Y Y Y=“XXXXXXXX”;END CASE;END PROCESS;END behavior;9奇偶校正LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY kk ISPORT (a:IN STD_LOGIC_VECTOR (4 DOWNTO 0);y:OUT STD_LOGIC);END kk;ARCHITECTURE arch OF kk ISBEGINPROCESS(a)VARIABLE temp:STD_LOGIC;BEGINtemp:=0; -偶校验初始值设为0，奇校验初始值设为1FOR i IN 0 TO 4 LOOPtemp:=temp XOR a(i);END LOOP;y=temp;END PROCESS;END arch; 9位奇偶校正LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY jou9 ISPORT( a:IN STD_LOGIC_VECTOR(8 DOWNTO 0);y:OUT STD_LOGIC);END jou9;ARCHITECTURE behavior OF ymq83 ISBEGINPROCESS(a) VARIABLE temp:STD_LOGIC;BEGIN temp:=1; FOR i IN 0 TO 8 LOOP temp:=temp XOR a(i); END LOOP;END PROCESS;y=temp;END behavior;10 移位寄存器双向移位寄存器 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ss IS PORT(clk:IN STD_LOGIC;dat_in:in std_logic;dat:in std_logic_vector(4 downto 0); outt:out std_logic_vector(4 downto 0) );END;ARCHITECTURE ONE OF ss IS signal x:std_logic_vector(4 downto 0):=01110;signal xx:std_logic_vector(4 downto 0);-signal cc:std_logic;BEGIN process(clk)beginif clkevent and clk=1 thenif dat_in=1thenx(4)=x(3);x(3)=x(2);x(2)=x(1);x(1)=x(0);x(0)=x(4);end if;if dat_in=0then x(0)=x(1);x(1)=x(2);x(2)=x(3);x(3)=x(4);x(4)=x(0);end if;end if;x=xx;end process;process(dat)begin xx=dat;end process;outt=x; END ONE; library ieee; use ieee.std_logic_1164.all; entity yiwei_r is port(ld:in std_logic; cp:in std_logic; d:in std_logic_vector(3 downto 0); q:buffer std_logic_vector(3 downto 0); end yiwei_r; architecture one of yiwei_r is begin process(ld,cp,d) variable aa:std_logic_vector(3 downto 0); begin if ld =1 then q=d; elsif cpevent and cp=1then aa(2 downto 0):=q(3 downto 1); aa(3):=q(0); q=aa; end if; end process; end one;循环左移位寄存器library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.STD_LOGIC_ARITH.ALL;use IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Vhdl1 IS PORT ( clk : IN std_logic; rst : IN std_logic; dataout : OUT std_logic_vector(7 DOWNTO 0); END Vhdl1;ARCHITECTURE arch OF Vhdl1 IS SIGNAL cnt : std_logic_vector(22 DOWNTO 0); SIGNAL dataout_tmp : std_logic_vector(7 DOWNTO 0); BEGIN dataout = dataout_tmp; PROCESS(clk,rst) BEGIN IF (NOT rst = 1) THEN cnt = 00000000000000000000000; dataout_tmp = 10011111; -为0的bit位代表要点亮的LED的位置 ELSIF(clkevent and clk=1)THEN cnt = cnt + 00000000000000000000001; IF (cnt = 11111111111111111111111) THEN dataout_tmp(6 DOWNTO 0) = dataout_tmp(7 DOWNTO 1); dataout_tmp(7) = dataout_tmp(0); END IF; END IF; END PROCESS;END arch;11 四位减法Library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity try isport (input1: in std_logic_vector( 3 downto 0);-beijianshu input2: in std_logic_vector( 3 downto 0);-jianshu over_led: out bit; led_tong: out bit;output_led: out std_logic_vector(0 to 6);end try;architecture arch of try issignal result:std_logic_vector(3 downto 0);beginprocess(input1, input2)beginled_tong input1)then over_led =1;-yichuresult =input2-input1;elseover_led=0;result output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led output_led = null;end case;end process;end arch;12 选择器lib