《数字逻辑设计》半期考试试题及参考答案.pdf

电子科技大学电子科技大学 2013-2014 学年第二学期学年第二学期 “数字逻辑设计及应用”“数字逻辑设计及应用”课程考试题 （半期） （120 分钟）考试日期 2014 年 4 月 27 日 一 二 三 四 五 六 七 八 九 十 总分 评卷教师 I. To fill the answers in the “( )” ( 2 X 15 = 30 ) 1. Given ABC F)5 , 4 , 1 (, then ABC F( 0, 2, 3, 6, 7 ), F = ABC( 1 ) + ABC( 0, 1 ). 2. ( 1001 0011 )8421BCD = ( 1111 0011 )2421BCD. 3. ( 0101 1101 )2 = ( 0111 0011 )Gray. 4. Open-drain output has two states, Low and ( Open 或 Hi-Z ). 5. A twos-complement = 0110 1010, C ones-complement = 1111 1011, A-Ctwos-complement = ( 0110 1110 ). Is it overflow for A-Ctwos-complement? (Yes or No) No 6. XOR gate in positive logic level is equivalent to ( XNOR ) gate in negative logic level. 7. Five variables can make ( 32 ) minterms. The sum of all the minterms must be ( 1 ). 8. If the function ABC F)6 , 3 , 2 , 1 (, then ABC F( 0, 4, 5, 7 ). 9. If the information bits are 1001 0010, the check bit is ( 0 ) for odd-parity. 10. To make 2014 code-words, ( 11 ) bits should be used at least. 11. Given the circuit shown in Figure 1, its output expression F = (ab+ac+bc 或 (b(a+c)+ac) ). Figure 1 II. There is only one correct answer in the following questions.( 3 X 10=30 ) 1. Which of the following codes has the self-complement property? ( D ) A. Gray B. Biquinary C. 8421BCD D. Excess-3 2. Which of the following 2-input gates can form a complete set of logic gates? ( B ) A. OR B. NOR C. XOR D. XNOR 3. Which of the following gates is equivalent to XNOR? ( A ) A. B. C. D. 4. Which of the following connection is correct? ( C ) A. B. C. D. 5. Which of the following expressions has no hazard? ( B ) A. F=W Y+W Z+X Y Z B. F=W Y+W Z+Y Z C. F=W Y+W Z+X Y Z+Y Z D. F=W Y+W Z+X Y Z+W X Y 6. Which of the following statements is correct? ( D ) A. The duality of the minimal sum expression is its minimal product. B. The minimum sum-of-product expression has no static-1 hazard. C. The canonical sum must have hazard. D. The minimum sum-of-product expression has no static-0 hazard. 7. The minimum sum of product for AB+AC+BCDEFGH is ( A ). A. A B+A C B. A B+A C C. A B+A C+B C D. A B+A C+B C 8. Given A=(0011 1111 . 0100)2, its equivalent values for A10 and A16 are ( B ) A. (96.58)10, (60.94)16 B. (63.25)10, (3F.4)16 C. (96.58)10, (60.49)16 D. (63.25)10, (3F.94)16 9. Given the timing diagram as shown in Figure 2, the output function is ( A ). A. xyz f)7 , 6 , 5 , 3( B. xyz f)4 , 2 , 1 , 0( C. xyz f)6 , 2 , 1 , 0( D. xyz f)7 , 2 , 1 , 0( Figure 2 10. A self-dual logic function is a function such that F=FD. Which of the following functions is self-dual? ( C ) A. xyz F)7 , 5 , 2 , 1 ( B. F = X Y Z+X Y Z+X Z C. F = X Y+X Z+Y Z D. )4 , 3 , 0( xyz F III. Combinational Circuit Analysis And Design: 40 1. Given F(A,B,C,D)= (BC B C)+A D (B C), the constraint condition is A (B+C)=0. Simplify the logic function F(A,B,C,D) into the minimal sum using Karnaugh map, and write out NAND-NAND logic expression of the minimal sum. (8) 参考评分标准： （1）填写 F 的卡诺图正确得 4 分，其中 d 占 1 分，错一格 扣 0.5 分，扣完为止。 （2）化简的表达式正确得 3 分，错一个乘积项扣 1 分。 Fminimal-sum (A,B,C,D) = BC+BD+CD （3） “与非-与非”表达式正确得 1 分。 FNAND-NAND (A,B,C,D) = (BC)(BD)(CD) 2. A combinational circuit is shown as below. (8) (1) Write out the sum-of-product expression of output F(W,X,Y,Z) for the circuit. (2) Analysis all conditions that the static hazard may exit for the circuit, and indicate types of static hazard. (3) Write out the minimal sum of output F(W,X,Y,Z) for the hazard-free. 参考评分标准： （1）表达式正确得 3 分，只要是正确的积之和形式就算对，不管是否为原始积之和，错一 个（或多一个或少一个）乘积项扣 1 分，扣完为止： F(W,X,Y,Z) = WXY+XYZ+XY （2）指出所有静态冒险及存在的条件得 2 分，其中指出静态冒险类型 1 分，具体如下： 当 W=Z=1，Y=0，X 变化时（1 分） ，存在静态 1 冒险（0.5 分） 当 X=Z=1，Y 变化时（1 分） ，存在静态 1 冒险（0.5 分） （只要描述正确就得分，不一定要画卡诺图。 ） （3）无冒险的最小和表达式正确得 2 分，错一个（或多一个或少一个）乘积项扣 0.5 分， 扣完为止。 F hazard-free (W,X,Y,Z) = WXY+WYZ+XY+XZ 3. Implement F(U,V,W,X,Y,Z) = U,V,W,X,Y,Z (3,5,7,19,23) using only a 74x138 and a NAND gate. (6) (1) Write out the canonical sum expression of F(U,V,W,X,Y,Z). (2) Draw the logic diagram. 参考评分标准： （1）F 的标准和表达式正确得 2 分，错一项扣 0.5，扣完为止。 F(U,V,W,X,Y,Z) = UVWXYZ + UVWXYZ + UVWXYZ + UVWXYZ + UVWXYZ （2）电路图输入正确得 2 分，输出正确得 2 分，错一处扣 0.5 分，扣完为止。 【答题提示：从第（1）小题写出的表达式可以看出，公因子是 UWZ，因此有 F(U,V,W,X,Y,Z) = UWZ (V XY+VXY+ VXY+VXY+VXY) 】 4. A combinational circuit is shown as below, which contains two 74x148 priority encoder and some gates. Input X9_L has the highest priority, and X0_L has the lowest priority. (8) (1) List out the truth table for the circuit. (2) Indicate the logic function of the circuit. 参考评分标准： （1）真值表正确得 6 分，错一行扣 1 分，扣完为止。 （2）电路功能描述正确得 2 分： 8421 BCD 优先编码器 （只写 BCD，未写 8421 的扣 1 分） 或者，写出正确的输出逻辑表达式也算正确： Y3 = X9_L + X9_L X8_L Y2 = X9_L X8_L X7_L + X9_L X8_L X7_L X6_L + X9_L X8_L X7_L X6_L X5_L + X9_L X8_L X7_L X6_L X5_L X4_L Y1 = X9_L X8_L X7_L + X9_L X8_L X7_L X6_L + X9_L X8_L X7_L X6_L X5_L X4_L X3_L + X9_L X8_L X7_L X6_L X5_L X4_L X3_L X2_L Y0 = X9_L + X9_L X8_L X7_L + X9_L X8_L X7_L X6_L X5_L + X9_L X8_L X7_L X6_L X5_L X4_L + X9_L X8_L X7_L X6_L X5_L X4_L X3_L X2_L X1_L 5. Design a converter circuit of Binary code (B3 B2 B1 B0) to Gray code (G3 G2 G1 G0) using only one 74x157 and some gates. Please select B2 as the selection input of 74x157. Please (1) Write out the four logic expressions of output G3, G2, G1, G0. (2) Draw the logic diagram. (10) （1）四个表达式正确得 6 分，每错一个表达式扣 1.5 分，扣完为止。 （仅真值表正确给 2 分，没有真值表不扣分） B3 B2 B1 B0 G3 G2 G1 G0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 1 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 1 0 1 0 1 1 1 1 1 0 1 1 1 1 1 0 1 1 0 0 1 0 1 0 1 1 0 1 1 0 1 1 1 1 1 0 1 0 0 1 1 1 1 1 1 0 0 0 （2）逻辑电路图总分 4 分，根据实际解题思