Lecture5简单数字电路设计-组合电路-v.ppt

Verilog HDL语言,华中科技大学计算机科学与技术学院,主讲：胡迪青 Email: QQ: 121374333,2,简单数字电路设计,3,设计验证与仿真,Verilog HDL不仅提供描述设计的能力，而且提供对激励、控制、存储响应和设计验证的建模能力。 激励和控制可用初始化语句产生。验证运行过程中的响应可以作为“变化时保存”或作为选通的数据存储。 最后，设计验证可以通过在初始化语句中写入相应的语句自动与期望的响应值比较完成。 要测试一个设计块是否正确，就要用Verilog再写一个测试模块。这个测试模块应包括以下三个方面的内容： 测试模块中要调用到设计块，只有这样才能对它进行测试； 测试模块中应包含测试的激励信号源； 测试模块能够实施对输出信号的检测，并报告检测结果。,4,Simulating/Validating HDL,The sad truth 10% design, 90% validation If you do it right you will spend 9X more time testing/validating a design than designing it.,5,Testbench Example (contrived but valid),module test_and; integer file, i, code; reg a, b, expect, clock; wire out; parameter cycle = 20; and #4 a0(out, a, b); / Circuit under test initial begin : file_block clock = 0; file = $fopen(“compare.txt“, “r” ); for (i = 0; i 4; i=i+1) begin (posedge clock) / Read stimulus on rising clock code = $fscanf(file, “%b %b %bn“, a, b, expect); #(cycle - 1) / Compare just before end of cycle if (expect != out) $strobe(“%d %b %b %b %b“, $time, a, b, expect, out); end / for $fclose(file); $stop; end / initial always #(cycle /2) clock = clock; / Clock generator endmodule,6,组合逻辑设计,组合逻辑电路 可以有若个输入变量和若干个输出变量，其每个输出变量是其输入的逻辑函数，其每个时刻的输出变量的状态仅与当时的输入变量的状态有关，与本输出的原来状态及输入的原状态无关，也就是输入状态的变化立即反映在输出状态的变化。 逻辑电路的各种运算可以用布尔代数来描述 狄摩根定律 利用狄摩根（DeMorgan）定律可以将积之和形式的电路转换为和之积形式的电路，或反之。,7,组合逻辑的三种通用表示方法 结构化（即门级）原理图 真值表 布尔方程式 实例：半加器,8,Combinational Circuits Component Instantiations,Circuit A connection of modules, Also known as structure A circuit is a second way to describe a,module, vs. using an always procedure, as earlier,Instance An occurrence of a module in a circuit May be multiple instances of a module, e.g., Cars modules: tires, engine, windows, etc., with 4 tire instances, 1 engine instance, 6 window instances, etc.,9,Combinational Circuits Module Instantiations,10,Combinational Circuits Module Instantiations,11,Combinational Circuits Module Instantiations,12,Combinational Circuit Structure Simulatingg the Circuit,Same testbench format for BeltWarn module as for earlier And2 module,13,Combinational Circuit Structure Simulatingg the Circuit,14,Combinational Circuit Structure Simulatingg the Circuit,timescale 1 ns/1 ns module Testbench(); reg K_s, P_s, S_s; wire W_s; BeltWarn CompToTest(K_s, P_s, S_s, W_s); initial begin,More on testbenches Note that a single module instantiation statement used reg and wire declarations (K_s, P_s, S_s, W_s) used because procedure cannot access instantiated modules,= 0; S_s P_s = 1; P_s = 1; P_s = 1;,= 0; S_s = 0; S_s = 0; S_s = 1;,K_s = 0; P_s #10 K_s = 0; #10 K_s = 1; #10 K_s = 1; end endmodule,ports directly Inputs declared as regs so can assign values (which are held between assignments) Note module instantiation statement,and procedure can both appear in one module,15,Combinational Behavior to Structure,16,Combinational Behavior to Structure Always Procedures with Assignment Statements,17,Combinational Behavior to Structure Procedures with Assignment Statements,Procedural assignment statement Assigns value to variable Right side may be expression of operators,timescale 1 ns/1 ns module BeltWarn(K, P, S, W); input K, P, S; output W; reg W;, Built-in bit operators include & AND | OR ,NOT,XOR,XNOR,always (K, P, S) begin W = K ,end,endmodule Q: Create an always procedure to compute:, F = CH + CH Answer 1: always (C,H) begin F = (C end,Answer 2: always (C,H) begin F = C H;,end,18,Combinational Behavior to Structure Procedures with Assignment Statements,Procedure may have multiple assignment statements,timescale 1 ns/1 ns module TwoOutputEx(A, B, C, F, G);,input A, B, C; output FF, G; reg F, G; always (A, B, C) begin F = (B end endmodule,19,Combinational Behavior to Structure Procedures with If-Else Statements,Process may use if-else statements (a.k.a. conditional statements), if (expression) If expression is true (evaluates to nonzero value), execute corresponding statement(s) If false (evaluates to 0), execute elsess statement (else part is optional) Example shows use of operator =,timescale 1 ns/1 ns module BeltWarn(K, P, S, W); input K, P, S; output W; reg W; always (K, P, S) begin if (K else,W = 0;,logical equality, returns true/false (actually, returns 1 or 0),end endmodule, True is nonzero value, false is zero,20,Combinational Behavior to Structure Procedures with If-Else Statements,More than two possibilities, Handled by stringing if-else statements together Known as if-else-if construct,Example: 4x1 mux behavior,timescale 1 ns/1 ns module Mux4(I3, I2, I1, I0, S1, S0, D); input I3, I2, I1, I0;,input S1, S0; output D;,Suppose S1S0 change to 01, Suppose S1S0 change to 01 ifs expression is false elses statement executes, which is an if statement whose expression is true,reg D; always (I3, I2, I1, I0, S1, S0) begin if (S1=0 ,else if (S1=1 ,Note: The following indentation shows if statement nesting, but is unconventional: if (S1=0 & S0=0),end endmodule,D = I0; else,if (S1=0 else,&,logical AND,& : bit AND (operands are bits, returns bit) & : logical AND (operands are true/false,if (S1=1 ,else D = I3;,values, returns true/false),21,Combinational Behavior to Structure Procedures with If-Else Statements,22,Combinational Behavior to Structure,23,Combinational Behavior to Structure Common Pitfall Missing Inputs from Event Control Expression,24,Combinational Behavior to Structure Common Pitfall Missing Inputs from Event Control Expression,Verilog provides mechanism to help avoid this pitfall, * implicit event control expression Automatically adds all nets and variables that are read by the controlled statement or statement group Thus, * in example is equival