InterfacialReactionInducedPBTIandNBTICharacteristicsintheHfNHfO2GateStackswithLowPreexistingTrapDensity【精品论文大全】.doc

精品论文推荐interfacial reaction induced pbti and nbti characteristics in the hfn/hfo2 gate stacks with low preexisting trap densityn. sa, h. yang, j.f. kang*1institute of microelectronics, peking university, beijing 100871, p.r. china,*e-mail: ;abstractin this paper, hfn/hfo2 gated n-fets and p-fets with low preexisting traps density in the hfn/hfo2 gate stacks were fabricated by using a high temperature process. the positive and negative bias temperature instability (pbti and nbti) characteristics in the hfn/hfo2 gate stacks are studied systematically. the characteristics of the vt instability mainly caused by the stress-polarity instead of the substrate type -dependent are observed both in n-fets and p-fets. the negative threshold voltage (vt) shifts, which can be well fitted by a generalized reaction-diffusion (r-d) model, are observed under both positive and negative bias temperature (nbt) stressing. the mechanisms of the interfacial reactions induced by the injected electrons or holes from substrates are proposed to explain the observed pbti and nbti characteristics: under pbt stressing, the injected electrons from the substrates induce the breaking of the si-o bonds in the interfacial layer between hfo2 layer and si substrates, which causes the pbti characteristics; under nbt stressing, the injected holes from the substrate induce the breaking of the si-h bonds at si interface, which causes the nbti characteristics. the consistency between the measured data and the ones predicted by the mechanisms confirms the validity of the interfacial reactions mechanisms. keywords: high-k gate dielectric, hfo2, negative-bias temperature instability (nbti), positive-bias temperature instability (pbti), reaction-diffusion (r-d) model- 8 -1introductionit is believed that metal/high-k gate stack will replace the poly-si/sio2 gate stack in 45 nm nodes and beyond to satisfy the stand-by power requirement without sacrificing metal oxide semiconductor field effect transistor (mosfet) performance 1. hfo2 is considered to be one of the most promising high-k candidates. an interfacial layer (il), composed mainly of sio2, between high-k layer and the si substrate is demonstrated to be inevitable and important for the performances of the mos devices such as the reliability 2. extensive investigation on the reliability of the hfo2 gate dielectrics has been widely studied. among the reliability issues, bias temperature instability (bti) characteristics have received more and more attention 3-10.the phenomenon that the shift of the threshold voltage or flatband voltage under gate bias and temperature stress is called the bias temperature instability (bti), which was first observed in sio2 based gate dielectrics 11. in the sio2 based gate dielectrics, most of the research on bti was focused on nbti since the nbti is much more significant than pbti 12. a generalized reaction-diffusion model was proposed to explain the mechanism of nbti in sio2 based gate dielectric 13. in the generalized reaction-diffusion model, the interfacial reaction induced by the injected hole from substrate is responsible for the nbti in the p-fets. the injected holes from substrate induce the breaking of the interfacial si-h bonds at si interface then the h (h+, h, or h2) species are released anddiffuse away into the dielectric layer. the diffused h species in dielectric layer may cause the creatingof bulk dielectric defects. the left interfacial states (si+) and the created dielectric defects cause the nbti. the shift of the threshold voltage caused by nbt has a fractional power-law dependence on the stress time. it has been shown that the t1/4-like time evolution is related with the diffusion of neutral species h, while the diffusion of charged species h+ is proposed to have a t1/2-like time evolution 13.for the high k gate dielectrics such as hfo2, both the significant pbti and nbti characteristics were observed 8.the mechanisms related to the holes and electrons trapping in the preexisting dielectric traps have been proposed to depict the pbti and nbti, respectively 5-8. for the pbti, most groups have reported positive threshold voltage shift and attributed it to electron trapping in preexisting dielectric traps 5-8. besides, the mechanism of the interfacial reaction like in sio2 was also proposed and demonstrated in the ald-hfo2 based gate dielectrics 3. a stretched exponential equation is proposed by zafar et al. to fit the experimental dada and nbti is also attributed to the h-related de-passivation of the sio2/si interface 4. with the pulsed id-vg method 14, more bulktraps have been demonstrated and a two-step negative u model was proposed to explain the electron trapping in pbti in high-k dielectrics 8.in this study, both n-fets and p-fets with the pvd-hfn/cvd-hfo2 gate stacks were fabricated, where the ultra thin hfn/hfo2 gate stacks with eot1.5 nm and the low preexisting charge trap density were deposited by using a high temperature process. the pbti and nbti characteristics of the hfn/hfo2 gate stacks were investigated systematically. we will report and demonstrate that, in the ultra thin hfn/hfo2 gate stacks with low preexisting charge trap density, both nbti and pbti characteristics could be attributed to the interfacial reaction mechanisms caused by the injected electrons or holes from substrates and can be well fitted with a generalized reaction-diffusion model. in the interfacial reaction mechanisms, the pbti is due to the breaking of si-o bonds dominated by the electric stress induced defect generation (esidg) mechanism 15 and the drift/diffusion of o- species under positive bias stressing 16; the nbti is due to the breaking of si-h bonds and the diffusion of h species under positive bias stressing.2 experimentsboth n-fets and p-fets with hfn/hfo2 gate stacks were fabricated using a gate-first process. after a dilute-hf (dhf)-last pre-gate clean, hfo2 films were deposited at 400c using a mocvd cluster tool followed by a 700oc in-situ post-deposition annealing (pda) in n2 ambient for 1 min. then pvd hfn (50nm) electrodes capped with pvd tan (100nm) were deposited by reactive sputtering in n2/ar mixture gas. after gate patterning by reactive ions etching (rie), source/drain (s/d) implantations of phosphorus for n-fets and bf2 for p-fets with a dose of 51015cm-2 were performed followed by rapid thermal annealing (rta) activation in n2 at 950oc for 30s. all devices were finally subjected to the forming-gas annealing at 420c for 30min. the equivalent oxide thickness (eot) of 0.95nm and1.3nm were extracted for n- and p-fet devices respectively, by using berkeley cv simulation program,taking into account the quantum mechanical correction 17. the id-vg curves are measured using direct current (dc) method. the vt is determined by the constant drain current method using a criterion of10-7a/cm. the constant voltage stress (cvs) measurements under various gate bias voltages atdifferent temperatures were made to evaluate the reliability characteristics.3experimental results and discussionfig. 1 shows the id-vg curves of the fresh n- and pfets using a double voltage sweep mode. the hysteretic vt changes of less than 10mv were measured both in the n- and p-fets devices, indicating the low preexisting traps in the hfn/hfo2 gate stack. the low preexisting traps in the hfn/hfo2 gate stack could be attributed to the high temperature post-gate annealing process such as the 950oc activation annealing process 18.10 -410 -610 -5i (a)d10 -710 -610 -710 -810 -810 -9nm o s fe t v =0 .1 vdpm o s fe t v =-0.1v d10 -910 -100.0 0 0.2 5 0.5 0 0.7 5 1.0-10.00 -0.75 -0.50 -0 .25 0 .00v (v )gv (v )gfig. 1 id-vg curves of the fresh devices for n- and pfets. negligible hysteresis (10mv) indicates the low preexisting charge traps in the hfn/hfo2 gate stack.a. polarity dependent bias temperature instabilitythe positive and negative bias stresses were applied on both the n-fets and p-fets at room temperature (rt). fig. 2 shows the comparisons of the id-vg curves of n- and p-fets before and after positive constant voltage stress (cvs=2.4v) at rt. the negligible vt shifts are observed after positivecvs for 2000 seconds.10 -3 10 -4 nm o s fe t10 -410 -5pm o s fe ti (a)d10 -5 a f t er 200 0s i (a)10 -6 v 10 m vth v 100m v10th 10c vs= -2 .4 v1000s rt10(a )1010-4pm osfet v 100m vthc vs=-2.4v2000srt (b)-5-6-7-8-9-10i (a)d-1.5 -1.0 -0.5 0.00.0 0.5 v (v ) 1.0 1.5gv (v)gfigure 3 id-vg curves of n- and pfets before and after negative cvs=-2.4v at rt.b. negative bias temperature instability in p-fetsthe dependence of vt on stressing time under constant voltage stress (-2.4v) and different temperatures for p-fets is shown in fig.4. the negative vt is observed. fig.5 is the dependence of relative shifts of subthreshold slope (s(t)/s(0) on the stressing time under the same constant voltage stress. the increased subthreshold slopes with stressing time imply the increased interfacial trap densityduring the nbt. fig.6 shows the increased hysteresis with stressing time, suggesting that new bulk charge traps have been generated during the nbt stressing. these results are near consistent with onesreported in ref. 3.-20-30v (mv)-40-50th-60-70-80-90-100rt125ocpmosfet cvs=-2.4v1101001000time(s)figure 4 dependence of vt on stress time under different temperature for pfets. the constant stress voltage is -2.4v098pmosfet cvs=-2.4v7s(t)/s (%)6125oc5 rt43211 10 1001000time(s)figure 5 dependence of s(t)/s(0) on stress time under negative bias for pfets10-410-5i (a)10-6fresh hysteresis10 mvd10-710-810-9after stress hysteresis37 mv-0.6-0.4-0.2v (v)gfigure 6 hysteresis of pfets before and after negative bias temperature process. obvious hysteresis increase is observed.c. positive bias temperature instability in n-fetsat room temperature, the pbti of n-fets is studied under different stress voltages and the results are shown in fig.7. negligible vt and a so-called “turn-around” phenomenon, which means positive vt shifts under low bias stressing and negative vt shifts under high bias stressing, are observed. the “turn-around” vt behaviors were ever reported 9, 10, and were speculated as the results of two competitive factors: one was electron trapping that dominates the process under low electric fields and low temperatures; the other was the generation and accumulation of positive charges that dominates the process under high fields and high temperatures. it was deduced that the generation and accumulation of positive charges under high fields and high temperatures was due to holes injection from poly-si gate and trapping in bulk dielectric layers or electron de-trapping from the preexisting charge traps. however, such mechanism could not explain the observed results as shown in fig. 7. one reason is that, it is not possible for holes to inject from hfn metal gate, therefore, the “turn-around” vt behaviors could not be related to the mechanism of the holes injection and trapping in the bulk dielectric layers; on the other hand, the positive shift of the threshold voltage is not enough for the counteraction of thefollowing negative vt shift. therefore, the theory of electron de-trapping cant be used here either.65room temperature43v (mv)21th0-1-2cvs=1.8v-3cvs=2.4v-4-5cvs=3.0v-61101001000time(s)figure 7 dependence of vt on stress time for nfets at room temperature under different stresses.negligible vt and the “turn-around” phenomenon are observed.fig.8 shows the pbti characteristics under various positive bias stressing at elevated temperature of 125. the significantly negative vt shifts are observed, which are also quite different from the recent published data 5-10 and can be speculated as the result of the accumulation of positive charges.in the same figure, the difference between the vt shifts under room temperature (rt) and those under125 can be clearly seen. compared to rt case, vt increases dramatically at 125 . the significant temperature-dependent vt shifts suggest that pbti is related to a thermal activation mechanism.0-30-60vth(mv)-90-120-150nmosfetcvs=3.0v rt cvs=2.0v 125oc cvs=2.4v 125oc cvs=3.0v 125oc1 10 1001000time(s)figure 8: dependence of vt on stress time at various pbt for nfets. pbti related to a thermal activation process is observed.fig.9 shows the shifts of the subthreshold slope (s) for the stressing times, voltages and temperatures, which is similar to the behavior of nbti as shown in fig.5. this suggests that during pbt stressing, new generation of interfacial trap states have also occurred at the interfaces between the dielectric layer and the substrates.10nmosfets/s (%)8cvs=3.0v rt cvs=2.0v 125 oc06cvs=2.4v 125 oc cvs=3.0v 125 oc4201101001000time(s)figure 9 dependence of s(t)/s(0) on stressing time at various pbt for nfets.stress induced leakage current (silc) is studied to inspect the change in bulk traps under various pbt. the dependence of silc on stressing time is shown in fig.10. the increasing ig suggests that bulk trap density increases during pbt.103i /i 0.5v (%)g102nmosfet101g010010-110-210-3cvs=3.0v rt cvs=2.0v 125 oc cvs=2.4v 125 oc cvs=3.0v 125 oc1101001000time(s)figure 10 dependence of gate leakage current on stressing time under various pbtbased on the above-mentioned results, we can conclude that under positive bias temperature stressing, positive charges accumulate at interface and/or in bulk layer, and interfacial and bulk traps increase at the same time.c. interfacial reaction-diffusion (r-d) modela generalized reaction-diffusion (r-d) model has been proposed to depict nbti characteristics ofhigh k p-fets with the following equation: 4v (t )vmax (1- exp (- (t / 0 ) ), whereuvmax, 0, , and are the fitting parameters. theparameter uvmaxis the maximum uvtx and is related to the total trap density, 0 is the characteristic time constant of the distribution in diffusion activation energy, and is a measure of distribution width.fig.11 shows the comparison of vt shifts of p-fets nbti between the ones measured andcalculated using the equation for the r-d mechanism. well agreements between measured andcalculated data with the fitting parameter 0.25 were observed. this suggests that nbti in thehfn/hfo2 gate stack could be attributed to the mechanism of the release of a neutral h atom from si-hbonds and the diffusion away from si interface caused by a stressing and holes induced reaction.- 9 -140120|v |(mv)10080th6040pmosfet=0.266125oc=0.22rtmeasuredcalculatedcvs=-2.4v201101001000time(s)figure 11 measured and calculated threshold voltage shifts for nbti. the fitting parameter is around0.25as the above discussions on pbti in n-fets, the possibility of both the electron-trapping mechanism that causes the positive vt shifts and the trapping of holes injected from the gate for the pbti observed in the study can be excluded. new mechanism is needed to explain the new observed pbti. fig.12 shows the comparisons of the vt shifts between measured and calculated data. themeasured data can be well fitted with the generalized r-d model. the extracted is about 0.6, whichcorresponds to the process of the drift/diffusion of charged species according to the generalized r-dmodel 13.100|v |(mv)th101nmosfetcvs=3.0v t=125 oc =0.55cvs=2.4v t=125 oc =0.58cvs=3.0v t=rt=0.630.1measuredcalculated1 10 1001000time(s)figure 12 comparison between measured and calculated results by the generalized r-d model with the fitting parameter 0.6.in the case of sio2 dielectrics, an electric stress induced defect generation (esidg) mechanismwas p