着名半导体公司DFTATPG内部培训资料.ppt

ATPG Introduction for IP Team,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage,Design Verification: Be sure the design perform its specified behavior. Before silicon. Testing: Exercise the system and analyze the response to ascertain whether it behaves correctly. After silicon. Diagnosis: To locate the cause of misbehavior after the incorrect behavior is detected. After silicon.,Whats DFT,DFT (Design For Test) Testability is a design attribute that measures how easy it is to create a program to comprehensively test a manufactured designs quality. Traditionally, design and test processes were kept separate, with test considered only at the end of the design cycle. But in contemporary design flows, test merges with design much earlier in the process, creating what is called a design-for-test (DFT) process flow. Testable circuitry is both controllable and observable. In a testable design; setting specific values on the primary inputs results in values on the primary outputs which indicate whether or not the internal circuitry works properly. To ensure maximum design testability, designers must employ special DFT techniques at specific stages in the development process.,Whats Structured DFT?,Structured DFT Provides systematic and automatic approach to enhancing design testability. Goal is to increase the controllability and observability of a circuit. Methods: scan design technique, which modifies the internal sequential circuitry of the design. Built-in Self-Test (BIST) method, which inserts a devices testing function within the device itself. boundary scan, which increases board testability by adding circuitry to a chip.,Whats ATPG,ATPG (Automatic Test Pattern Generation) Test patterns (test vectors), are sets of 1s and 0s placed on primary input pins during the manufacturing test process to determine if the chip is functioning properly. ATE (Automatic Test Equipment) determines if the circuit is free from manufacturing defects by comparing the fault-free outputwhich is also contained in the test patternwith the actual output measured by the ATE. Goal : create a set of patterns that achieves a given test coverage. Then run it on Tester. Pass indicated no related defects exist in this chip.,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage,SCAN Cell / SCAN Chain,Scan Cell In normal operation (sc_en = 0), system data passes through the multiplexer to the D input of the flip-flop, and then to the output Q. In scan mode (sc_en = 1), scan input data (sc_in) passes to the flip-flop, and then to the scan output (sc_out). Scan Chain A set of serially linked scan cells. Each scan chain contains an external input pin and an external output pin that provide access to the scan cells. The scan chain length (N) is the number of scan cells within the scan chain.,SCAN Procedure,The operating procedure of the scan circuitry is as follows: 1. Enable the scan operation to allow shifting (to initialize scan cells). 2. After loading the scan cells, hold the scan clocks off and then apply stimulus to the primary inputs. 3. Measure the outputs. 4. Pulse the clock to capture new values into scan cells. 5. Enable the scan operation to unload and measure the captured values while simultaneously loading in new values via the shifting procedure (as in step 1).,Before Scan,After Scan,SCAN Waveform,scan_clk,scan_se,SCAN Types,Full Scan Highly automated process. Highly-effective, predictable method. Ease of use. Assured quality. Partial Scan Reduced impact on area. Reduced impact on timing. More flexibility between overhead and fault coverage. Re-use of non-scan macros.,Stuck-At Fault Model,Example: Single Stuck-At Faults for AND Gate The single stuck-at model is the most common fault model used in fault simulation, because of its effectiveness in finding many common defect types. The stuck-at fault models the behavior that occurs if the terminals of a gate are stuck at either a high (stuckat-1) or low (stuck-at-0) voltage. The fault sites for this fault model include the pins of primitive instances. All s-a-0 faults in the AND gate are equivalent,s-a-1 s-a-0,s-a-1,s-a-0,s-a-1 s-a-0,s-a-1,s-a-1,s-a-0,s-a-1,Possible Errors: 6,Possible Errors: 4,Stuck-At Coverage Report,# DT - Test Coverage = #FU - #UU - #TI - #BL - #RE # DT - Fault Coverage = #FU,Statistics report - #faults #faults fault class (coll.) (total) - - - FU (full) 1171003 1824936 - - - UC (uncontrolled) 32 84 UO (unobserved) 946 1286 DS (det_simulation) 3580 8011 DI (det_implication) 4 10 (protected) 1138170 1767804 PU (posdet_untestable) 784 1806 PT (posdet_testable) 34 42 UU (unused) 3035 5344 TI (tied) 2093 2201 BL (blocked) 331 333 RE (redundant) 8272 10462 AU (atpg_untestable) 13722 27553 - - - test_coverage 98.66% 98.30% fault_coverage 97.50% 97.31% atpg_effectiveness 99.91% 99.92% - - - Protected Faults alone: test_coverage 98.35% 97.85% fault_coverage 97.20% 96.87% - #test_patterns 271 #simulated_patterns 271 CPU_time (secs) 18364.6 -,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage,Combinational Loop & Tri-state But,Combinational Loop Notice that the A=1, B=0, C=1 state causes unknown (oscillatory) behavior, which poses a testability problem. It should be avoid if possible. Tri-state Bus Contention Tri-state Bus is not permitted inside chip.,Divided Clock,Some designs contain uncontrollable clock circuitry; that is, internally-generated signals that can clock, set, or reset flip-flops. If these signals remain uncontrollable, they could disturb sequential elements during scan shifting. Thus, the system cannot convert these elements to scan. new_clk = scan_mode? tst_clk : gen_clk,Async Reset,Test Logic Added to Control Asynchronous Reset use ipt_async_se to control the mux. new_rst = ipt_se_async_xxx? ext_rst : int_rst,Async Reset (2),For the case where both set and reset of a flop are internally generated, either set or reset shall be disabled during scan mode using “ipt_mode_scan“ signal, while other can be muxed with hardreset using “ipt_se_async“ signal. Selection of disabling set/reset signal shall be decided having less combinational logic for getting better test coverage.,Clock Gating,Clock Gating When clk is pulsed from low to high, the latch is disabled and remains so as long as the clk signal stays high. Therefore, even if the output of dff1 changes from high to low as a result of the leading edge of the pulse, that value change cannot propagate through the latch and effect clk_en until clk goes low again, enabling the latch. Equally important, scan chains must operate correctly. You can force se to 1 in the load_unload procedure; however, it must be done before any “apply shift” statement. The se signal must be controllable to 1 from the chips primary inputs (IC pins). In IP DFT guide this se signal is connected to ipt_se_gatedclkp.,Clock Gating (2),Clock Gating Cell,CP,E+TE,QD,Q,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in Scan Scan cell Scan chain Scan procedure Scan waveform Scan type Scan fault model Scan Coverage,DFT Signals,DFT signals Ipt_mode_scan_xxx Ipt_se_xxx Ipt_se_async_xxx Ipt_se_gatedclkn/p_xxx Ipt_si/so_xxx,Ipt_dbg_tck_xxx Ipt_dbg_trst_xxx Ipt_dbg_tms_xxx Ipt_dbf_tdi_xxx Ipt_dbg_tdo_xxx,Please refer to Section 2.3 of ,Agenda,DFT Rules Combinational Loop Asynchronous Reset Tri-state Bus Contention Clock Dividers Clock Gating DFT signals For Scan For debug Soft IP tasks and deliverables Scripts and Demos Q&A,Whats it? DFT Structured DFT ATPG Terminology in S