《IC制造流程简介》PPT课件.ppt

IC制造流程简介 ANDY,相关定义,半导体是指导电能力介于导体和非导体之间的材料，其指四价硅中添加三价或五价化学元素而形成的电子元件，它有方向性可以用来制造逻辑线路使电路具有处理资讯的功能。 半导体的传导率可由搀杂物的浓度来控制：搀杂物的浓度越高，半导体的电阻系数就越底。 P型半导体中的多数载体是电洞。硼是P型的掺杂物。 N型半导体的多数载体是电子。磷，砷，锑是N型的搀杂物。,相关定义,集成电路是指把特定电路所需的各种电子元件及线路缩小并制作在大小仅及2CM平方或更小的面积上的一种电子产品。,相关定义,集成电路主要种类有两种：逻辑LOGIC及记忆体MEMORY。前者主要执行逻辑的运算如电脑的微处理器后者则如只读器READ ONLY 及随机处理器RANDOM ACCESS MEMORY等。集成电路的生产主要分三个阶段：硅镜片WAFER的制造，集成电路的制造及集成电路的包装PACKAGE,Wafer Start,CMP,Oxidation PVD, CVD,Wafer Cleaning,Photolithography,Etch (Dry or Wet),Annealing,Implantation,The Outline,Wafer Start,CMP,Wafer Cleaning,製程,The Introduction to The Manufacturing Process of VLSI,ANDY,晶圓(Wafer),晶棒成長 切片(Slicing) 研磨(Lapping),清洗(Cleaning) 拋光(Polishing) 檢查(Inspection),Melt,Seed,Graphite Crucible,Growing Crystal,Noncontaminating Liner,(a) Seed being lowered down to melt,(b) Seed dipped in melt freezing on seed just beginning,(b) Partially grown crystal,The Czochralski Method - 1,(a) As-grown crystal,(b) Grind crystal to remove undulations and saw to remove portions in resistive range,(c) Saw into slices (with orienting flats ground before sawing),(d) Round edges of slice by grinding,(e) Polish slice,Crystal to Wafe,微影(Photolithography),原理： 在晶片表面上覆上一層感光材料，來自光源的平行光透過光罩的圖形，使得晶片表面的感光材料進行選擇性的感光。 感光材料： 正片經過顯影(Development)，材料所獲得的圖案與光罩上相同稱為正片。 負片如果彼此成互補的關係稱負片,Wafer,Wafer,Contact Print to expose resist,Wafer,Resist,Apply resist after priming (spinner),Resist,Oxide,Light source,Projection print to expose resist,or,Wafer,Resist,Oxide,Projection lens,Mask,Condenser lens,Next Page,Photolithography Process - 1,Mask,Continue,Wafer,Wafer,Wafer,Develop resist,Etch oxide,Strip resist,Developed resist showing pattern,Etch to match resist pattern,Resist removed,Photolithography Process - 2,Doping: To get the extrinsic semiconductor by adding donors or acceptors, which may cause the impurity energy level. The action that adding particular impurities into the semiconductor is called “doping” and the impurity that added is called the “dopant”.,Introduction to Doping,Doping methods: 1.Diffusion 2.Ion Implantation,Pre-deposition: To put the impurities on the wafer surface. Generally used dopant resource furnace design:,Carrier gas,Heater,Quartz tube,Solid dopant source furnace,O2,Liquid dopant source,Carrier gas,Gas dopant source,Valve,O2,(a),(c),(b),Diffusion Process - 1,Solid dopant source,Drive-in: To implant the dopant into the wafer by the thermal process,Quartz tube,Quartz tube,Heater,Wafer,Gas out,Reaction room,Gas in,Gas out,Wafer,Quartz boats,3-Zone heating element,Dopants and gas in,Profiling Tc (In the tube),Horizontal Type,Vertical Type,Diffusion Precess - 2,1. The definition: A manufacturing process that can uniformly implants the ions into the wafer in the specified depth and consistence by selecting and accelerating ions. 2. The purpose: To change the resistance value of the semiconductor by implanting the dopant. 3. Energy range (8 years ago) (1) General process：10 KeV - 180 KeV (0.35m) (100KeV for 0.18 m now) (2) Advanced process：10 KeV - 3 MeV (0.5m) (3) R&D process：0.2 KeV - 5 KeV,Introduction to Ion Implantation,Dopant Source,Ion Source,Mass Analysis,Accelerator,Scanner,Electron Shower,Ion Implanter,Extractor,Farady Cap,Parameters Doping elements selection Scanning uniformity control Temperature control Concentration control,Factors The selection of the ion resource The design of the mass analyzer Scanning system Vacuum control Precise wafer position control Precise and stable electric power supplier The measurement of the ion current (Farady Cup),Doping Parameters,Physical Vapor Deposition,DC,Metal Target,Gas In,To The Vacuum Pump,Wafer,Plate,Collimator,Chemical Vapor Deposition,(a) Reagents diffuse through the interface boundary layer (b) Adsorbed onto the wafer surface (c) Deposition reaction happens (d) Byproducts diffuse through the interface boundary layer (e) Reagents & byproducts pass away,Heat Source,(a) (d) (b) (c),(e),Reaction,Main Stream Interface Boundary Layer Wafer surface,Vacuum System,(1) Thermal Oxidation The growth temperature is above 900 0C. High quality SiO2. (2) Low Pressure CVD (LPCVD) The growth temperature is around 400 0C to 750 0C. Better step coverage ability. (3) Plasma Enhanced CVD (PECVD) The growth temperature is under 400 0C. In the case of the Al deposition and non-thermal process.,Solutions to Deposition,Down Force,wafer,Wafer Carrier,Carrier Film,Slurry,Carrier,Wafer,Interconnects,Composite Pad,Table,Polishing Pad,Polishing table,p,CMP System Schematic,Carrier Film,c,Major Parameters In CMP,SiO2 CMP: Down Force Rotating Speed (p) Type of The Pad Metal and Si CMP: pH Measurement,* The lower the force-speed ratio the better the planarity,Slurry,Particle (0.1 2.0 um) Silica (Colloidal) Alumina (Dispersed) Liquor (Contains some oxidant and organic reagents in the case of metal CMP) KOH NH4OH,Wafer Cleaning,Purpose: To remove the remains and impurities,Methods: Brush Cleaning Spray Cleaning Ultrasonic Cleaning,Photo resist,SiO2,Si Substrate,PhotoMask,Positive Resist,Negative Resist,Etching Intro - 1,Next Page,Positive Resist,Negative Resist,Etching Intro - 2,Continue,Etching Methods,Wet Etching (Isotropic) Relatively simple process High throughput Low quality Dry Etching (Anisotropic) High quality (due to the excellent pattern transfer ability) Worse selectivity,Wet Etching,Substrate,Thin Film,Solution,Boundary Layer,Reagent,Resultant,Reaction,Photo Resist,(a) Isotropic Etching：A=0 (Erh=Erv),(b) Anisotropic Etching：A=1 (Erh=0),Isotropic & Anisotropic,Quartz dome,Silicon wafer,Silicon carbide coated graphite,RF Coil,Gas in,Gas exit,Silicon carbide susceptor,Gas exit,Silicon wafers,RF induction heating coil,Dry Etching