基于FPGA新型步进电机控制器硬件实现外文翻译.doc

基于fpga新型步进电机控制器硬件实现daniel carrica, senior member, ieee, marcos a. funes, and sergio a. gonzlez, member, ieee摘要：本文提出了一种新颖的基于现场可编程门阵列的步进电机控制器，这种控制器呈现出了显著的优势。 该系统提供了一种新型算法和可编程逻辑的组合，以达到硬件工作既高速又精确。关键字：现场可编程门阵列（ fpga ） ，运动控制，步进电机。.引言在高精度步进电机应用中，使用小步距电动机是非常必要的，其尺寸是由实际需求决定的。另一个可供选择的技术是微步技术，其电机步长通过控制进一步的减小。由于微步与很小的位移有关，因此必须由大量微步求得总位移。而总位移必须在可接受的时间内执行。因此，微步之间的时间差应该尽量减小。当以微步的运作方式分度时，控制器和驱动器之间的高速数据传输是必须的。此外，开环编码器比那些闭环编码器要便宜的多，如果选择开环系统，则必须使用速度分布图，以避免失去步进功能的后果。图1显示了一台步进电机的基本构成。它有三个部分：1）速度分布图生成器；2)分度器；3)电流驱动装置。(1)和(2)被置在了我们称之为控制器的里面。在速度分布图生成以后，必须由分度器把他们转变为成脉冲时间间隔。每个分度脉冲意味着电机在一个步进中转子的位置必须增加的量，因此命名其为分度器。这个模块的功能就是完成从速度到时间的转化。这个模块可以看作是对电机动作增加量的的控制，而其他类型的电机只可以通过应用速度分布图以电流或电压的形式控制1,2。图.1.完整控制系统图1中的控制器的实施有两个不同的选择：离线或上线配置。离线：在离线配置中，微步的时间比动作3和4先计算出来了。速度分布和脉冲之间的时间跨度被计算出来后，存放在一些记忆媒介的硬件中，例如rom甚至硬盘。这些配置有一个缺点，就是它们对组成记忆器和记时器得硬件容量有很严格的要求，这个容量要与电机的数量以及位移的范围与精确度相适应。上线：智能系统通过时间滞后序列产生的算法来执行计算分度器脉冲的操作。在图2中可以看到一个基本配置的流程图。这个流程图包含两个主要模块：部分表示速度分布图的建立和的计算、当前的步骤和接下来一步之间的时间的计算。也就是，是速度分布图发生器，是分度器。因为是用一个单一的方程计算速度分布图和，因此有一个共同的模块是共享的。例如，（1）和（2）为梯形分布图5表达了一个典型的算法。 （1） （2）这儿是最终速度，是电机的最高速度，是微步的总数，是梯形分布图的加速度，是第步的时间。这些配置以及离线的配置为了获得脉冲分度而利用了计时器。因此每台电机配置一台计时器是很有必要的，但当必须由一个处理器来控制多台电机的时候，这种方法就往往不令人满意了。另一个很严重的缺点是计算（1）时需要计算时间，而对速度有影响。此外，不仅影响（3）中的最大速度，而且计时器分辨率也影响着（3）中的最大速度。 （3）当计时器的分辨率足够小时，以至于可以摒弃方程中的。因此，（3）转变为了（4）。图.2.上线算法 （4）当速度很高时，标准算法将失效，这主要是因为要计算时间。为了解决速度的问题，下面提供一个更有效的没有计时器的步进发生程序的新算法。.算法的提出本节所提出的算法可以解释如下：为了估计时间，假设是倍的，则这是一个不使用计时器的测量时间的精确的方法。因此，在每一次迭代中，所提出的算法要做好以下步骤：1） 使2）假设 （5）其中，是一个正整数。3）检验：如果假设允许期望。则，这意味着 （6）其中，是在第步进时的速度。图.3.算法流程图4）如果第三步检验通过，那么执行新的步进。否则，增加并且重复这一过程。（2，3和4） （7）从（5）可以看出，的分辨率是。（6）中的等式因为这个分辨率而不可能成立，等式（6）相应的变成了（8） （8）消除（8）中的则必须减少迭代时间。因此，一个简单的缩写式（9）就成了首选。 （9）新算法是基于（5）、（7）和（9）之上的，（5）中的与（4）中的有相同的意义，但是相关的数量更少，因此此处的计算是很简单。实验表明此种方法计算比传统的算法要小10倍。图.4.预期速度分布图总括来说，该算法基本上是一定时期的累计直到达到预期速度。图3.表示了执行（5）、（7）和（9）的一个系统的流程图。速度分布图模块在之前就已经执行了。通过（5）可以得到， 是一个整数，则新算法的的分辨率是。新算法中分辨率出现了一个速度量化问题，因为在（6）中速度与是成反比的。由于是的整数倍，而且，结果表明，该速度指令有以下特点 （10）下面举一个例子，图.4显示了从开始到有一个最大速度的梯形分布图。为了保持预期速度的轨道（在间断线），该系统定义初始值。这个速度最接近预期的初速度。在时刻，变到6，作为一个结论，我们知道会产生更高的速度。在时刻，产生一个指令速度。然后在时刻，指令速度为，与期望速度分布相等。当在速度比较高时，比小，量化的影响更显著。影响效果也可以解释为中间的速度不能发生在与、与以及与之间等等。图.5. 基于fpga的控制系统因此，这个算法既不需要计时器，也不需要查找表，并且可以在很高的速度下应用。它的缺点是量化会产生一定的影响，这个量化取决于的数量。由目前的dsp技术，最小微妙。这个的数量在速度大约为15000步进/每秒产生的量化水平为2000步进，这表明了问题的严重性。. 硬件实现为了减少计算的时间，硬件的实现问题被提了出来。第二节提出的算法由传统的硬件就很容易实现。硬件允许多个任务并行执行，因此，可以提供一个有效的并行执行的方法，这个方法可以大大减少计算时间。例如：分布图发生器、乘法器以及分度器可以分别由不同的模块彼此独立的执行。这时方程（5）和（9）为（11）所取代，虽然，这意味着算法没有发生改变，但它使得两个乘数变为一个，这就使得高效率的硬件实现起来没有缺点。在图5.中表示了（5）和（9）的硬件实现，框图表示的是控制器。计时钟周期的计数器描绘了（5）的执行。（11）的硬件实现是由乘法器和比较器实现的。 （11）当不等式成立时，产生一个新的步进。信号随之被传输到驱动程序接口，从而控制脉冲给电机的每个相位驱动。图5.显示了一个四相位电机。该硬件实现的时钟周期，等于软件执行第二节中的算法的时间。该时钟周期决定了控制器的时间分辨率。因为在硬件实现中，可以在很大程度上得以降低，因此，量化对速度的影响可以忽略不计。标准的乘法器的执行是由一个组合结构完成的。这种做法非常好的考虑了时间，因为它提出了一种由逻辑门产生的最小延迟，但它占用了大量的逻辑资源，从而增加了乘数字长度的比例。例如，一个1616位的乘积需要占用一个由10000逻辑门组成的fpga 6,7的 90的逻辑资源。为了克服fpga领域的问题，在8和9中为乘数按序排出序列。这种做法可以让一个有效范围减图.6.基于fpga系统的位置和速度分布图少10倍，但是却有更大的，如一个16位的乘数就需要配置16个时钟脉冲。不过对一个40 mhz的时钟来说，时间只有400纳秒了，对于系统仍然可以忽略不记。作为一个结论，采用连续乘数时，在一个fpga系统中，算法的实现有6000个逻辑门。生成梯形分布图时也会生成几个参数，如加速度，最小速度和最大速度，以及步进数量。控制器决定基于这些参数分布图，并生成一个参考分布来驱动步进电机。于是基于新算法的一个新的控制器的硬件实现提出来了。新系统提供了一个在简洁的硬件上就可以实现既高速度又高精度的方案。此外，由于具有弹性和fpga实现能减少计算时间的特点，这个控制器可以很容易的实现全步模式、半步模式和微步模式驱动。 . 实验结果为了评价系统的绩效，在一个xilinx fpga xc40063里执行了提出的算法。这个装置拥有6000个逻辑门，可以在同步系统时钟频率高达80 mhz时运行。实验中使用了一个混合式步进电机。该电机特点：400步进/转，惯性力矩为1310-7kgm2， nm。再没有额外的相联系的工作负荷了。位置测量的获得是通过增量光学编码器elap-e521获得的，elap-e521有一个1024脉冲/转的分辨率，其惯性力矩为2.5106kgm2。这是通过一个惯性力矩为2.3106kgm2的helical-wa25相互联系在一起的。位置曲线是通过译码器读高分辨率的计时器信号获得的。通过离线状态的位置来获得速度分布图。乘数器以一个40 mhz的时钟率工作，产生一个400纳秒的时间。纳秒是可以接受的，在相应的电机速度里，仍然是可以忽略不计的。在生成梯形分布图后，步进电机必须建立12000步进位移，该梯形分布图有以下特征：步进/s，步进/s和最大加速度步进/s2。由此产生的速度和位置数据可以从图.6中看出。低时间可以允许几乎是连续分布和很高的速度，比那些标准软件算法所产生的更高。由于分布图的特点，步进电机在中间区域5降低。这种效果可以在低速的分布图中观察到。图.7显示在完全步进的高速所得到的完全分布。注意其在所有有效速度范围内的连续性。图.7.基于fpga系统的速度分布图图.8显示了一个微步应用的完全分布。在此实验中使用的是一个slo-syn kml093f14c5步进电机，其特点是：200步进/转，支持扭矩为n cm以及回转惯性为3.32kgcm2。位置值是通过具有500脉冲/转的分辨率的光学增量式编码器获得的。该微步驱动模块使用的是slo-synmd808，其配置为2000脉冲/转。作为一个结论，该系统必须产生步进/每秒，步进/每秒以及最大加速度步进/每秒的平方的高速度分布图。为了降低速度从到1000步进/秒的跳跃，时间采用400纳秒，因此，速度跳跃仍然在的5以内。这个结果可以从分布图上面的波纹组成观察到。该系统取得了非常高的速度，这是处理器执行的标准算法无法达到的速度。此外，新的控制器不再需要常规系统中必需的计时器，处理器也由一个类似大小和成本的fpga取代。图.8.微步应用的速度分布图.结论本文介绍了一种减少操作数量的新颖的算法。该算法在fpga上实施，实现了大幅下降典型速度控制器里必须的等效处理时间。实验证明，步进电机可以达到非常高的速度，而且这种速度是无法通过基于系统的标准算法实现的。由于该系统的体系结构，一个fpga可以同时驱动几个步进电机而不增加处理时间。它可以用具有6000个逻辑门的fpga驱动3个步进电机。这一优势使得该系统非常方便，只要简单地用一个更大的fpga就可以增加电机的数目。附：英语原文novel stepper motor controller based on fpgahardware implementationdaniel carrica, senior member, ieee, marcos a. funes, and sergio a. gonzlez, member, ieeeabstractthis paper proposes a novel stepper motor controller based on field programable gate arrays, showing a remarkable performance.the system provides a combination between a novel algorithm and programmable logic to achieve both high speed andhigh precision on a compact hardware.index termsfield programable gate arrays (fpga), motioncontrol, stepper motor.i. introductionin high precision stepper motor applications, it is necessary to use motors with small steps whose size is imposed by the required resolution. another alternative is the technique of microstepping, where the motor step size is further reduced by means of control. as microsteps are related to very little displacements,a great quantity of microsteps are required to get the total displacement. total displacement should be executed in an acceptable time. as a consequence, the time between microsteps should be reduced. a high-speed data transmission between controller and driver is mandatory when indexing in microstepping mode of operation.furthermore, open loop applications are much less expensive than close loop ones due to encoders. if open loop is chosen, velocity profiles have to be used in order to avoid the step lose effect.a general system for the commanding of a stepper motor is shown in fig. 1. there are three functions: 1) the velocity profile generation block; 2) the indexer; and 3) the power drivers. blocks (1) and (2) are embedded in what we named controller.after velocity profiles are generated, they have to be translated into pulse intervals by the indexer. each index pulse means that the motor must increment its rotor position in one step/microstep, hence the name indexer. this block functions as a velocity-to-time translator. this block is unique to the commanding of incremental motion devices since other types of motors can be commanded just by applying the velocity profile in form of current or voltage 1, 2.fig. 1. complete control system.the implementation of the controller of fig. 1 can be performedby two alternatives: off-line or on-line schemes.a. off-linein the off-line schemes the timing of the steps/microsteps is calculated prior the movement 3, 4. the velocity profile and the time space between pulses are calculated and then stored in some kind of memory media bundled into the hardware, i.e., rom or even hard drives.a disadvantage of these schemes is that they require an important hardware volume, composed of memories and timers. this volume is proportional to the quantity of motors and the extension and precision of displacements.b. on-linean intelligent system carries out the operation of calculating the index pulses through a time lagging sequence generation algorithm. in fig. 2 a flowchart of one basic scheme can be seen. this flowchart contains two main blocks: construction, where the velocity profile is actually developed, and calculation, where the time between the current step and the next is calculated. that is, is the velocity profile generation and is the indexer of fig. 1. often a common block is shared because a single equation computes both the velocity profile and the . for example, (1) and (2) express a typical algorithm for a trapezoidal profile 5. （1） （2） where is the resulting speed, is the maximum speed of the motor, is the total number of steps or microsteps, is the acceleration of the trapezoidal profile and is the time of the -th step.these schemes as well as the off-line ones make use of timers for obtaining the indexed pulses. since it is necessary one timer per motor, this approach is often discouraged when multiple motors have to be commanded by a single processor.another important disadvantage is the computing time , requiredto compute (1). imposes a practical limit to the speed. moreover, not only tc but the timer resolution, tr affect the maximum speed as in (3) （3）fig. 2. on-line algorithms.current timer resolutions are small enough to discard the at the equation. therefore, (3) turns into (4) （4）standard algorithms fail to reach high speeds, mainly because the computing time, . in order to resolve the goal is to provide a new algorithm with a more effective step generation procedure without timers.ii. proposed algorithmthe proposed algorithm can be explained as follows. in order to estimate the time , it is assumed that is times , since it is an accurate way of measuring time without using timers. therefore, the proposed algorithm has to do the following functions during each iteration: 1) let 2) assume （5）where is a positive integer number.fig. 3. flow chart of the algorithm.3) verify if assumed allows the wished . thus, it means （6）where is the reference velocity at the -th step.4) if the verification is true, then execute the new step/microstep. if not, then increment and repeat the process. (points 2, 3, and 4) （7）from (5) it can be seen that the resolution of is . the equality in (6) is not possible because of this resolution. equation (6) becomes the comparison stated in (8) （8）eliminating the division in (8) is mandatory for reducing the iteration time. therefore a simple contraction as in (9) is preferred （9）the new algorithm is based on (5), (7), and (9). in (5) has the same meaning as in (4), but with a considerable smaller magnitude, since the computations here are very straightforward. it is experimentaly demonstrated that ten times less than in conventional algorithms is achieved.fig. 4. intended velocity profile.to conclude, the algorithm consists basically on a periodic accumulative sum until the intended velocity is reached. fig. 3 shows the flowchart of a system that implements (5), (7) and (9). the velocity profiles block was previously executed.from (5), resolution of the new algorithm is since is an integer. resolution in the newalgorithm arises to a velocity quantization problem because velocity is the inverse of (6). since the term is a multiple of and , it turns out that the speed commanded has the following characteristics: （10）as an example, fig. 4 shows a trapezoidal profile which starts at and has a maximum . in order to keep track of the intended speed (in discontinuous line), the system commands an initial value of .this results in an initial speed of which is the closest possible speed to the intended initial speed, . at , changes to 6. as a consequence a higher speed of occurs. at , produces a commanded speed of . it then follows that at time the commanding speed is which equals the intended velocity profile.the quantification effect is more remarkable at higher speeds when times are smaller as . the effect can also be explained since intermediate speeds cannot take place between and , or between and , nor among and , etc.fig. 5. fpga based control system.therefore, an algorithm has been developed which requires neither timers nor lookup tables and can work for much higher speeds. its disadvantage is the quantification effect which depends on the magnitude of . with current dsp technology, a minimum s is obtainable. this magnitude produces a quantification level of 2000 steps at speeds arround 15 000 steps/s, which shows the importance of the problem.iii. hardware implementationin order to reduce the computing time, a hardware implementation is proposed. the algorithm presented in section ii is simple enough to be executed by a custom hardware. hardware implementation permits multiple parallel tasks, thus, providing an effective way of implementing true parallelism which allows a great reduction of computing time because operations such as the reference profile generation, multipication and indexation can be executed in separate blocks and can run independently ones of the others.equations (5) and (9) are replaced by (11) . although, this means no changes in the algorithm, it reduces the pair of multiplications to only one. this fact allows an efficient hardware implementation without performance demerit. hardware implementation of (5) and (9) is presented in fig. 5, wherethe block diagram of the controller is shown. the counter, wich counts clock periods, represents the execution of (5). the hardware implementation of (11) is carried out by themultiplier and the comparator （11）when the inequation is satisfied, a new step is commanded. the signal is then fed to the driver interface, which commands the pulses to the driver of each motor phase. fig. 5 shows a four phase motor.the clock period of hardware implementation is equivalent to the computing time in the software execution of the algorithm of section ii. the clock period defines the time resolution of the controller. as can be well reduced in hardware approach, the quantizacion effect on the mechanical velocity will be negligible.fig. 6. position and velocity profile with the fpga based system.standard implementation of a multiplier is accomplish by acombinatorial structure. this approach is very good regarding the time because it presents a minimum delay imposed by the logic gates, but it involves a great number of logic resources, which increase proportionally with the multiplier word length. as an example, a 16 16 bits product requires the 90% of a 10 000 logic gates fpga 6, 7. in order to overcome the fpga area problem, a sequential arquitecture for the multiplier is proposed 8, 9. this approach allows an effective area reduction of 10 times, but with a greater , i.e., 16 clock pulses for a 16-bit word multiplier. however, with a 40 mhz clock, time is only 400 ns which remains neglicted for system performance. as a consequence, a sequential multiplier was adopted, which permited the implementation of the algorithm in a fpga of 6000 logic gates.a trapezoidal profile is generated, with several parameters, such as acceleration, minimum and maximum speed, and step quantity. the controller decides how the profile must be based on these parameters, and generates a reference profile to drive the stepper motor.as a conclusion, a new controller based on a novel algorithm implemented by hardware was proposed. the new system provides a good combination to achieve both high speed and high precision motion on a compact hardware. furthermore, this controller can easily drive full, half and micro-step mode applications due to the flexibility and the reduced computing time with the fpga implementation.iv. experimental resultsto evaluate the performance of the system, the developed algorithm was implemented in a xilinx fpga xc40063. this device can run at synchronous system clock rates up to 80 mhz、and has a capacity 6000 logic gates. a hybrid stepping motor was used in the experiments. motor characteristics: 400 step/rev, inertial moment 1310-7kgm2， nm. no aditional load was connected.fig. 7. velocity profile with the fpga based systemthe position measures were obtained through an incremental optical encoder elap-e521 with a resolution of 1024 pulses/rev whose inertial moment is2.5106kgm2. it was coupled through an helical-wa25 with an inertial moment of 2.3106kgm2 .the position curve was obtained by reading the encoder signal with a high resolution timer. the position was off line derived to obtain the speed profile.the muliplier works with a 40-mhz clock rate, which yield a multiplication time of 400 ns. ns was adopted, wich remains negligible in relation to the motor speed.the stepper motor must develop a 12 000 step displacement following a reference trapezoidal profile with charasteristics: steps/ s, steps/ s and a max acceleration steps /s .the resultant speed and position profiles can be seen in fig. 6. the low time allows an almost continuous profile and very high speeds, higher than those generated by standard software algorithms. due to the characteristic of the profile, the stepper motor passes through resonance area 5. this effect can be observed at low speeds in the profiles.fig. 7 shows a complete profile obtained at high speeds with full step. note the continuity at all the effec