《Laker使用教程》PPT课件.ppt

P.1,IC Layout Tool Laker & Candace,SSCAS Pin-Dai Sue,P.2,Outline,Laker Base Operate .P3 Candace Base Operate .P11 Virtuoso Base Operate P14 DRC CheckP18 LVS Check.P22 PEX.P27 Matching.P31,P.3,Laker Create New Library,Library New,Define Library Name,Chose Technology File,P.4,Laker Create New Cell,Cell New,Chose Library,Defined Cell Name,P.5,Laker Tool Interface,Layer Table,Create Rectangle Hot key: r,Create Polygon Hot key: Shift + p,Create Path Hot key: p,Create text Hot key: l,Create Instance Hot key: i,Move Hot key: m,Stretch Hot key: s,Copy Hot key: c,Delete Hot key: Delete,Reshape Hot key: Shift + r,Chop Hot key: Shift + c,Merge Hot key: Shift + m,Split Hot key: Ctrl + s,Measure Distance Hot key: d,Attribute Hot key: q,Zoom Out Hot key: Shift + z,Zoom In Hot key: Ctrl + z,Zoom All Hot key: f,P.6,Laker Layer Level,Sub,Diff,Poly1,Metal1,Metal2,Metal3,Metal4,Metal5,Metal6,Contact,VIA12,VIA23,VIA34,VIA45,VIA56,P.7,Laker Create Contact,Create Contact Hot key: o,P.8,Laker - Create Transistor,Create Transistor Hot key: Ctrl + m,P.9,Laker Example PMOS,PMOS,Symbol,Layout View,NIMP,PIMP,NWELL,P.10,Laker Example NMOS,NMOS,Layout View,NIMP,PIMP,Symbol,P.11,Laker Example Inverter,Inverter Layout,INV Schematic,INV Layout,Create text Hot key: l,Key in pin name,P.12,Candace Open Library Manager,Tools Library Manager,All Library,Sub Cell,Cell View,Candace Create New Library,File New Library,Defined Library Name,Key in Technology File Path,1.,2.,3.,P.14,Candace Create New Cell (Schematic),File New Cell View,1.,Chose Library,Define Cell Name,Chose Cell View,2.,P.15,Schematic Tool Interface,Check and Save Hot key: Shift + x,Save Hot Key: Xhift + s,Zoom In By 2,Zoom Out By 2,Stretch Hot key: s,Copy Hot key: c,Delete Hot key: Delete,Undo Hot key: u,Property Hot key: q,Instance Hot key: i,Wire (narrow) Hot key: w,Wire (wide) Hot key: Shift + w,Wire Name Hot key: l,Pin Hot key: p,Cmd Options,Repeat,P.16,Schematic Create Component (1/2),Instance Hot key: i,Example: pmos4,P.17,Schematic Create Component (2/2),Define parameter,Example:,Cell: vdd,Cell: gnd,Cell: nmos4,Cell: pmos4,Cell: cap,Cell: res,P.18,Schematic Example Inverter,Wire (narrow) Hot key: w,Pin Hot key: p,Define Pin Name,P.19,DRC Check Open DRC,Check layout layer rule,P.20,DRC Check Define DRC Rule,Choose DRC Rule,1.,2.,3.,4.,P.21,DRC Check Define DRC Rule,Error Table,Axis,Error Message,1.,2.,3.,4.,P.22,DRC Check Highlight Error,P.23,LVS Check Open LVS,Against with layout and schematic,P.24,LVS Check Define LVS Rule,1.,2.,3.,4.,Choose LVS Rule,P.25,LVS Check Define Netlist File,Choose Netlist File,Chose Cell,1.,2.,3.,4.,5.,6.,7.,P.26,LVS Check NO Error,P.27,LVS Check Error,Error Table,Error Message,Layout,Netlist,P.28,PEX Open PEX,P.29,PEX - Define PEX Rule,1.,2.,4.,3.,P.30,PEX Define Netlist File,1.,2.,3.,4.,5.,6.,7.,P.31,PEX PEX Result,P.32,Matching Resistor Matching,R1,R2,80k,80k,R1,R2,R1,R2,R1,R2,20k,80k,R1,R2,R1,R2,40K,40K,40K,40K,40k+40k,40k+40k,40k+40k,40k / 40k,P.33,Matching Capacitor Matching,C1=0.2p,C2=0.2p,C1,C2,C2,C1,0.1p,0.1p,0.1p,0.1p,C1=0.8p,C2=0.1p,C1,C1,C1,C1,C2,C1,C1,C1,C1,0.1p / 0.1p,0.1p / 0.1p,P.34,Matching MOS Matching (1/3),80m/1m,G,S,D,B,P.35,Mat