大量的verilog源代码.docx

Verilog HDL 程序举例一，基本组合逻辑功能：双向管脚（clocked bidirectional pin）Verilog HDL: Bidirectional PinThis example implements a clocked bidirectional pin in Verilog HDL.The value of OE determines whether bidir is an input, feeding in inp, or a tri-state, driving out the value b.bidir.v module bidirec (oe, clk, inp, outp, bidir);/ Port Declarationinput oe;input clk;input 7:0 inp;output 7:0 outp;inout 7:0 bidir;reg 7:0 a;reg 7:0 b;assign bidir = oe ? a : 8bZ ;assign outp = b;/ Always Constructalways (posedge clk)begin b = bidir; a = inp;endendmodule多路选择器（MUX）/-/ DESCRIPTION : Multiplexer/ Code style: used case statement/ Width of output terminal: 8/ Number of terminals: 4/ Output enable active: HIGH/ Output value of all bits when enable not active: 0/-module mux(EN ,IN0 ,IN1 ,IN2 ,IN3 ,SEL ,OUT ); input EN ; input 7:0 IN0 ,IN1 ,IN2 ,IN3 ; input 1:0 SEL ; output 7:0 OUT ; reg 7:0 OUT ; always (SEL or EN or IN0 or IN1 or IN2 or IN3 ) begin if (EN = 0) OUT = 81b0; else case (SEL ) 0 : OUT = IN0 ; 1 : OUT = IN1 ; 2 : OUT = IN2 ; 3 : OUT = IN3 ; default : OUT = 81b0; endcase endendmodule二进制到BCD码转换 / /-/ DESCRIPTION : Bin to Bcd converter/ Input (data_in) width : 4/ Output (data_out) width : 8/ Enable (EN) active : high/-module bin2bcd (data_in ,EN ,data_out );input 3:0 data_in ;input EN ;output 7:0 data_out ;reg 7:0 data_out ; always (data_in or EN ) begin data_out = 81b0; if (EN = 1) begin case (data_in 3:1) 3b000 : data_out 7:1 = 7b0000000; 3b001 : data_out 7:1 = 7b0000001; 3b010 : data_out 7:1 = 7b0000010; 3b011 : data_out 7:1 = 7b0000011; 3b100 : data_out 7:1 = 7b0000100; 3b101 : data_out 7:1 = 7b0001000; 3b110 : data_out 7:1 = 7b0001001; 3b111 : data_out 7:1 = 7b0001010; default : data_out 7:1 = 71b0; endcase data_out 0 = data_in 0; end endendmodule二进制到格雷码转换 /-/ DESCRIPTION : Bin to gray converter / Input (DATA_IN) width : 4/ Enable (EN) active : high/-module BIN2GARY (EN ,DATA_IN ,DATA_OUT ); input EN ; input 3:0 DATA_IN ; output 3:0 DATA_OUT ; assign DATA_OUT 0 = (DATA_IN 0 DATA_IN 1 ) & EN ; assign DATA_OUT 1 = (DATA_IN 1 DATA_IN 2 ) & EN ; assign DATA_OUT 2 = (DATA_IN 2 DATA_IN 3 ) & EN ; assign DATA_OUT 3 = DATA_IN 3 & EN ;endmodule7段译码器/-/ DESCRIPTION : BIN to seven segments converter/ segment encoding/ a/ +-+ / f | | b/ +-+ - g/ e | | c/ +-+/ d/ Enable (EN) active : high/ Outputs (data_out) active : low/-module bin27seg (data_in ,EN ,data_out ); input 3:0 data_in ; input EN ; output 6:0 data_out ; reg 6:0 data_out ; always (data_in or EN ) begin data_out = 7b1111111; if (EN = 1) case (data_in ) 4b0000: data_out = 7b1000000; / 0 4b0001: data_out = 7b1111001; / 1 4b0010: data_out = 7b0100100; / 2 4b0011: data_out = 7b0110000; / 3 4b0100: data_out = 7b0011001; / 4 4b0101: data_out = 7b0010010; / 5 4b0110: data_out = 7b0000011; / 6 4b0111: data_out = 7b1111000; / 7 4b1000: data_out = 7b0000000; / 8 4b1001: data_out = 7b0011000; / 9 4b1010: data_out = 7b0001000; / A 4b1011: data_out = 7b0000011; / b 4b1100: data_out = 7b0100111; / c 4b1101: data_out = 7b0100001; / d 4b1110: data_out = 7b0000110; / E 4b1111: data_out = 7b0001110; / F default: data_out = 7b1111111; endcase endendmodule二，基本时序逻辑功能：8位数据锁存器 /-/ DESCRIPTION : Flip-flop D type/ Width : 8/ CLK active : high/ CLR active : high/ CLR type : synchronous/ SET active : high/ SET type : synchronous/ LOAD active : high/ CE active : high/-module ffd (CLR , SET , CE , LOAD , DATA_IN , DATA_OUT , CLK );input CLR , SET , CE , LOAD , CLK ;input 7:0 DATA_IN ;output 7:0 DATA_OUT ;reg 7:0 DATA_OUT_TEMP; always (posedge CLK ) begin if (CE = 1b1) if (CLR = 1b1) DATA_OUT_TEMP = 81b0; else if (SET = 1b1) DATA_OUT_TEMP = 81b1; else if (LOAD = 1b1) DATA_OUT_TEMP = DATA_IN ; end assign DATA_OUT = DATA_OUT_TEMP;endmodule移位寄存器/-/ DESCRIPTION : Shift register/ Type : univ/ Width : 4/ Shift direction: right/left (right active high)/ CLK active : high/ CLR active : high/ CLR type : synchronous/ SET active : high/ SET type : synchronous/ LOAD active : high/ CE active : high/ SERIAL input : SI/-module shft_reg (CLR , SET , DIR , CE , LOAD , DATA , SI , data_out , CLK );input CLR , SET , CE , LOAD , DIR , SI , CLK ;input 3:0 DATA ;output 3:0 data_out ;reg 3:0 TEMP; always (posedge CLK ) begin if (CE = 1b1) if (CLR = 1b1) TEMP = 41b0; else if (SET = 1b1) TEMP = 41b1; else if (LOAD = 1b1) TEMP = DATA ; else if (DIR = 1b1) TEMP = SI , TEMP 3:1; else TEMP = TEMP 2:0, SI ; end assign data_out = TEMP;endmodule三，基本语法，元件例化与层次设计：Verilog HDL: Creating a Hierarchical DesignThis example describes how to create a hierarchical design using Verilog HDL. The file top_ver.v is the top level, which calls the two lower level files bottom1.v and bottom2.v.vprim.v top_ver.v module top_ver (q, p, r, out);input q, p, r;output out;reg out, intsig;bottom1 u1(.a(q), .b(p), .c(intsig);bottom2 u2(.l(intsig), .m(r), .n(out);endmodule-bottom1.v module bottom1(a, b, c);input a, b;output c;reg c;alwaysbegin c=a & b;endendmodule-bottom2.v module bottom2(l, m, n);input l, m;output n;reg n;alwaysbegin n=l | m;endendmodule四，状态机举例：同步状态机Verilog HDL: Synchronous State Machinestatem.v module statem(clk, in, reset, out);input clk, in, reset;output 3:0 out;reg 3:0 out;reg 1:0 state;parameter zero=0, one=1, two=2, three=3;always (state) begin case (state) zero: out = 4b0000; one: out = 4b0001; two: out