基于vhdl的电子闹钟设计.doc

基于VHDL的数字闹钟设计摘要：随着EDA技术的发展和应用领域的扩大与深入，EDA技术在电子信息、通信、自动控制及计算机应用领域的重要性日益突出。EDA技术就是依赖功能强大的计算机，在EDA工具软件平台上，对以硬件描述语言VHDL为系统逻辑描述手段完成的设计文件，自动地完成逻辑优化和仿真测试，直至实现既定的电子线路系统功能。本文介绍了基于VHDL硬件描述语言设计的多功能数字闹钟的思路和技巧。在Quartus 11开发环境中编译和仿真了所设计的程序，并逐一调试验证程序的运行状况。仿真和验证的结果表明，该设计方法切实可行，该数字闹钟可以实现调时定时闹钟播放音乐功能具有一定的实际应用性。关键字：闹钟 FPGA VHDL Quartus II一、电子钟相关功能描述如下：(1) 计时功能：这是本计时器设计的基本功能，可进行时、分、秒计时，并显示。(2) 闹钟功能：如果当前时间与设置的闹钟时间相同，则扬声器发出一段音乐，并维持一分钟。(3) 调时调分调闹钟功能：当需要校时或者要重新设置闹钟的时间时，可通过实验箱上的按键控制。二、设计原理：数字闹钟电路的基本结构由两个60进制计数器和一个24进制计数器组成，分别对秒、分、小时进行计时，当计时到23时59分59秒时，再来一个计数脉冲，则计数器清零，重新开始计时。秒计数器的计数时钟CLK为1Hz的标准信号。当数字闹钟处于计时状态时，秒计数器的进位输出信号作为分钟计数器的计数信号，分钟计数器的进位输出信号又作为小时计数器的计数信号时、分、秒的计时结果通过6个数码管来动态显示。数字闹钟除了能够正常计时外，还应能够对时间进行调整。因此，通过模式选择信号KEY1、KEY2控制数字钟的工作状态，即控制数字钟，使其分别工作于正常计时，调整分、时和设定闹钟分、时5个状态。当数字闹钟处于计时状态时，3个计数器允许计数，且秒、分、时计数器的计数时钟信号分别为CLK,秒的进位, 分的进位;当数字闹钟处于调整时间状态时，被调的分或时会一秒一秒地增加；当数字钟处于闹钟定时状态时，可以设定小时和分；当计时到所设定的时刻时，speak将会被赋予梁祝音乐信号用于驱动扬声器，持续1分钟。三、实验代码：1）顶层文件：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY clock IS PORT ( CLK12MHZ : IN STD_LOGIC; CLK8HZ : IN STD_LOGIC; SPKOUT : OUT STD_LOGIC; CLK : IN STD_LOGIC; KEY1 : IN STD_LOGIC; KEY2 : IN STD_LOGIC_VECTOR(1 DOWNTO 0); H1,H2,M1,M2,S1,S2: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); END;ARCHITECTURE one OF clock IS COMPONENT shizhong PORT (clk : in std_logic; md1 : in std_logic; md2 : in std_logic_vector(1 downto 0); clken : out std_logic; h1,h2,m1,m2,s1,s2: out std_logic_vector(3 downto 0); END COMPONENT; COMPONENT NoteTabs PORT ( clk : IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) ); END COMPONENT; COMPONENT ToneTaba PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); en : in std_logic); END COMPONENT; COMPONENT Speakera PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC ); END COMPONENT; SIGNAL Tone :STD_LOGIC_VECTOR (10 DOWNTO 0); SIGNAL ToneIndex :STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL clken :STD_LOGIC; SIGNAL en :STD_LOGIC; BEGINu1 : Shizhong PORT MAP (clk=CLK,md1=KEY1,md2=KEY2,clken=en, h1=h1,h2=h2,m1=m1,m2=m2,s1=s1,s2=s2);u2 : NoteTabs PORT MAP (clk=CLK8HZ, ToneIndex=ToneIndex);u3 : ToneTaba PORT MAP (Index=ToneIndex,Tone=Tone,en=en);u4 : Speakera PORT MAP (clk=CLK12MHZ,Tone=Tone, SpkS=SPKOUT );END;2）时钟控制模块：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity shizhong isport( clk: in std_logic; md1:in std_logic; md2:in std_logic_vector(1 downto 0); clken:out std_logic; h1,h2,m1,m2,s1,s2:out std_logic_vector(3 downto 0);end shizhong;architecture one of shizhong issignal hou1:std_logic_vector(3 downto 0);signal hou2:std_logic_vector(3 downto 0);signal min1:std_logic_vector(3 downto 0);signal min2:std_logic_vector(3 downto 0);signal seth1:std_logic_vector(3 downto 0);signal seth2:std_logic_vector(3 downto 0);signal setm1:std_logic_vector(3 downto 0);signal setm2:std_logic_vector(3 downto 0);signal sec1:std_logic_vector(3 downto 0);signal sec2:std_logic_vector(3 downto 0);begin-小时十位h110:process(clk,hou2,min1,min2,sec1,sec2,md1,md2)beginif clkevent and clk=1 thenif (hou1=0010 and hou2=0011)and(min1=0101 and min2=1001) and (sec1=0101 and sec2=1001) thenhou1=0000;elsif hou1=0010and hou2=0011and md1=0 and md2=01 then-当时间为23点且处于校时状态时hou1=0000;elsif (hou2=1001and(min1=0101 and min2=1001) and (sec1=0101 and sec2=1001)or (hou2=1001and md1=0 and md2=01) thenhou1=hou1+1;end if;end if;end process h110;-小时个位h220:process(clk,min1,min2,sec1,sec2,md1,md2,hou1)beginif clkevent and clk=1 thenif (hou1=0010 and hou2=0011)and(min1=0101 and min2=1001) and (sec1=0101 and sec2=1001) thenhou2=0000;elsif hou2=1001and(min1=0101 and min2=1001) and (sec1=0101 and sec2=1001) thenhou2=0000;elsif (hou2=1001and md1=0 and md2=01)or (hou1=0010and hou2=0011) thenhou2=0000;-md=1;-elsif (min1=0101 and min2=1001) and (sec1=0101 and sec2=1001)or (md1=0 and md2=01) thenhou2=hou2+1;-speak=clk;-end if;end if;end process h220;-分钟十位 m110:process(clk,min2,sec1,sec2,md1,md2)beginif clkevent and clk=1 thenif (min1=0101 and min2=1001) and (sec1=0101 and sec2=1001) then min1=0000;elsif min1=0101and min2=1001and (md1=0 and md2=00)thenmin1=0000;elsif (min2=1001and (sec1=0101 and sec2=1001) or (min2=1001and md1=0 and md2=00)thenmin1=min1+1;end if;end if;-end if;end process m110;-分钟个位 m220:process(clk,sec1,sec2,md1,md2)beginif clkevent and clk=1 thenif min2=1001and (sec1=0101 and sec2=1001)thenmin2=0000;elsif min2=1001and (md1=0 and md2=00)thenmin2=0000;else if (sec1=0101 and sec2=1001) or(md1=0 and md2=00)thenmin2=min2+1;end if;end if;end if;end process m220;-秒十位 s110:process(clk)beginif clkevent and clk=1 thenif (sec1=0101 and sec2=1001)thensec1=0000;else if sec2=1001thensec1=sec1+1;end if;end if;end if;end process s110;-秒个位 s220:process(clk)beginif clkevent and clk=1 thenif sec2=1001 thensec2=0000;else sec2=sec2+1;end if;end if;end process s220;-时间设置小时部分 sethour1:process(clk,seth2)beginif clkevent and clk=1 thenif seth1=0010and seth2=0011 thenseth1=0000;elsif seth2=1001 thenseth1=seth1+1;end if;end if;end process sethour1;sethour2:process(clk,md1,md2,seth1)beginif clkevent and clk=1 thenif (seth1=0010and seth2=0011)or seth2=1001thenseth2=0000;elsif md1=1 and md2=00 thenseth2=seth2+1;end if;end if;end process sethour2;-时间设置分钟部分 setmin1:process(clk,setm2)beginif clkevent and clk=1 thenif setm1=0101and setm2=1001thensetm1=0000;elsif setm2=1001thensetm1=setm1+1;end if;end if;end process setmin1;setmin2:process(clk,md1,md2)beginif clkevent and clk=1thenif setm2=1001thensetm2=0000;elsif md1=1 and md2=01thensetm2=setm2+1;end if;end if;end process setmin2;-闹铃speaker:process(clk,hou1,hou2,min1,min2)beginif clkevent and clk=1thenif seth1=hou1 and seth2=hou2 and setm1=min1 and setm2=min2 thenclken=1;else clken=0;end if;end if;end process speaker;disp:process(md1,hou1,hou2,min1,min2,sec1,sec2,seth1,seth2,setm1,setm2)beginif md1=0 then-计时时间显示和设置模式h1=hou1;h2=hou2;m1=min1;m2=min2;s1=sec1;s2=sec2;else -闹铃时间现实和设置模式h1=seth1;h2=seth2;m1=setm1;m2=setm2;s1=1111;s2=1111;end if;end process disp;end one;3）乐曲演奏模块：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY Speakera IS PORT ( clk : IN STD_LOGIC; Tone : IN STD_LOGIC_VECTOR (10 DOWNTO 0); SpkS : OUT STD_LOGIC );END;ARCHITECTURE one OF Speakera IS SIGNAL PreCLK, FullSpkS : STD_LOGIC;BEGIN DivideCLK : PROCESS(clk) VARIABLE Count4 : STD_LOGIC_VECTOR (3 DOWNTO 0) ; BEGIN PreCLK 11 THEN PreCLK = 1; Count4 := 0000; ELSIF clkEVENT AND clk = 1 THEN Count4 := Count4 + 1; END IF; END PROCESS; GenSpkS : PROCESS(PreCLK, Tone)- 11位可预置计数器 VARIABLE Count11 : STD_LOGIC_VECTOR (10 DOWNTO 0);BEGIN IF PreCLKEVENT AND PreCLK = 1 THEN IF Count11 = 16#7FF# THEN Count11 := Tone ; FullSpkS = 1; ELSE Count11 := Count11 + 1; FullSpkS = 0; END IF; END IF; END PROCESS; DelaySpkS : PROCESS(FullSpkS)-将输出再2分频，展宽脉冲，使扬声器有足够功率发音 VARIABLE Count2 : STD_LOGIC;BEGIN IF FullSpkSEVENT AND FullSpkS = 1 THEN Count2 := NOT Count2; IF Count2 = 1 THEN SpkS = 1; ELSE SpkS = 0; END IF; END IF; END PROCESS;END;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY NoteTabs IS PORT (clk : IN STD_LOGIC; ToneIndex : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) );END;ARCHITECTURE one OF NoteTabs ISCOMPONENT MUSIC -音符数据ROM PORT(address : IN STD_LOGIC_VECTOR (7 DOWNTO 0); inclock : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END COMPONENT; SIGNAL Counter : STD_LOGIC_VECTOR (7 DOWNTO 0);BEGIN CNT8 : PROCESS(clk,Counter) BEGIN IF Counter=138 THEN Counter = 00000000; ELSIF (clkEVENT AND clk = 1) THEN Counter Counter , q=ToneIndex, inclock=clk); END;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY ToneTaba IS PORT ( Index : IN STD_LOGIC_VECTOR (3 DOWNTO 0) ; Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0); en : IN STD_LOGIC);END;ARCHITECTURE one OF ToneTaba ISBEGINPROCESS(Index,en) BEGINIF en=0 THEN Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone Tone NULL; END CASE;END IF; END PROCESS;END;LIBRARY ieee;程序USE ieee.std_logic_1164.all;LIBRARY altera_mf;USE altera_mf.altera_mf_components.all;ENTITY music ISPORT( address: IN STD_LOGIC_VECTOR (7 DOWNTO 0);inclock: IN STD_LOGIC ;q: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END music;ARCHITECTURE SYN OF music ISSIGNAL sub_wire0: STD_LOGIC_VECTOR (3 DOWNTO 0);COMPONENT altsyncramGENERIC (intended_device_family: STRING;width_a: NATURAL;widthad_a: NATURAL;numwords_a: NATURAL;operation_mode: STRING;outdata_reg_a: STRING;address_aclr_a: STRING;outdata_aclr_a: STRING;width_byteena_a: NATURAL;init_file: STRING;lpm_hint: STRING;lpm_type: STRING);PORT ( clock0: IN STD_LOGIC ;address_a: IN STD_LOGIC_VECTOR (7 DOWNTO 0);q_a: OUT STD_LOGIC_VECTOR (3 DOWNTO 0);END COMPONENT;BEGINq Cyclone,width_a = 4,widthad_a = 8,numwords_a = 256,operation_mode = ROM,outdata_reg_a = UNREGISTERED,address_aclr_a = NONE,outdata_aclr_a = NONE,width_byteena_a = 1,init_file = data1.mif,lpm_hint = ENABLE_RUNTIME_MOD=YES, INSTANCE_NAME=rom2,lpm_type = altsyncram)PORT MAP ( clock0 = inclock, address_a = address, q_a = sub_wire0