PON-MAC芯片BL2000介绍.doc

上海爱启企业服务有限公司 是一家专门为企业服务的公司，主要从事企业登记注册，财务咨询，代理记账，出口退税，用友财务软件及财务培训等。企业服务qq群号：274061401PON MAC芯片（DS-BL2000）介绍1、主要接口1.1数字接口l Dual Fast Ethernet 10/100 (IEEE 802.3/802.3u)l Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)l Native TDM GEM Interfacel Peripheral Bus Interface (PBI) for glueless interface to common industry1.2光接口n Integrated 2488/1244Mbps CDRn Glueless interface to BPON and GPON Multi-Source Agreement (MSA) Small Form Factor (SFF) transceivers1.3 TDM接口n TDM Interfacen Native TDM over GEM via an companion FPGA2、以太网MAC2.1配置以太网接口l Fast Ethernet 10/100 (IEEE 802.3/802.3u)MII or dual RMII MAC InterfaceHalf and full duplex supportl Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)GMII MAC Interfacel Configurable 802.3x hardware flow controll IEEE 802.1q VLAN tagging2.2、GPON MACl The GPON MAC supports Ethernet packet and TDM payload transport over the PON interface through GPON Encapsulation Mode (GEM). It supports ITU-T G.984.x set of standards with extended functionalitiesl Compliant to G.984.xl Multiple data ratesl Configurable AES encryption on DS payloadl Configurable FEC on US and DS payloadl Dedicated connections for In-band management can be directed to CPU2.3、BPON MACBroadLights ITU-T G.983 MAC is industry proven and FSAN interoperable.l G.983.1 compliantl G.983.2 (OMCI) compliantl G.983.4 (DBA) compliantl Multiple data ratesl Queue managerl 32 VP/VC group filtersl ATM cell processing with end-to-end OAM per I.610l Derives clock from recovered network clock2.4、CDR, SerDesl PCML TX and LVPECL RX interface levelsl Variable Data ratesl Selectable reference clock frequency 78 MHz or 155 MHzl Integrated on-chip 50 termination resistor in the transmitter and in the receiver3、Cell/Packet Processor信源、包处理引蟼是为了优化GPON或者BPON数据平台流处理器。信源、包处理引蟼包括：AAL5-SAR，AAL2-SAR，802.1d-bridge学习，ATM整形和策略。包含核心处理和硬件加速器，在时钟频率为200MHz可达到300K packets/s。3.1固件l Supports up to 100 Mbps full duplex sustained Ethernet traffic with 64-byte packetsl Support for 512 filtering table entriesl Support for 802.1p, 802.1q and 802.1Dl ATM cell processing and Ethernet packet processing using AAL5 adaptation methodl Support of RFC-2684 with VC multiplexing or LLC encapsulation3.2硬件l 32-bit instructions and register data widthl Thirty two general purpose registersl 16 KB instruction address spacel 48 KB memory data spacel 256 addresses for I/O data space (used by HW accelerators)l Several data addressing modesl 32-bit ALU and 32-bit shift unitl Byte mask operationsl 32-bit accumulator register used as output for each part of the execution unitl Special instructions for activating HW accelerators and networking purposes such as scheduling4、核心处理单元The BL2000s embedded CPU is a general purpose MIPS32 based controller that provides control plane functionality for the ONT system and for PON operation。5、MIPS子系统l 32-bit 4KEc RISC corel 16 KB I-Cache, 8 KB D-Cachel Memory Management Unit (MMU)l Single-stepping of the processor as well as instruction and data virtual address beakpoints via EJTAG6、系统接口单元（SIU）6.1 Programmable General Purpose I/O (GPIO)l 21 Bidirectional General Purpose I/Ol 3.3 V tolerant inputsl TTL/Open collector outputsl 4mA current to drive LEDs6.2 Peripheral Bus Interface (PBI)l 24-bit address bus clocked up to 66 MHzl Configurable bus clock (BUSCLK): rates of 20 MHz, 25 MHz, 33 MHz, 50 MHz, and 66 MHzl Configurable wait states of up to 20 BUSCLK cyclesl Peripheral byte access supportl Support for asynchronous and synchronous bus accessesl Configurable assertion, de-assertion, and polarity for CS, RW, and TS6.3 Interrupt Controllerl Servicing up to 6 edge or level external sources and 21 internal sources.l Different interrupt priority levels l Programmable priority level and mask per interrupt source6.4 UARTl 32-Byte buffersl Selectable baud rate from 9600 Bytes115.2 KBytes6.5 I2Cl Master transmitter and receiverl 32-Byte buffersl Support of inter-bit and inter-byte clock stretching6.6 Serial Peripheral Interface (SPI)l Limited to control plane applicationsl Operation in master model Full duplex master transmit/receive6.7 Timersl Configurable SW watchdog timerl Three general purpose 32-bit timers6.8 Power Managementl Sleep mode (Outgoing Calls Only)l Low Power Mode (Lifeline)6.9 External Memoryl 200 MHz DDR2 SDRAMl 16-bit data bus6.10 JTAGl IEEE 1149.1 compliant, JTAG boundary scan7、物理层说明1. Voltagesl Core 1.2V 5%l I/O 2.5V 0.2V (3.3V tolerant)l DDR 1.8V 0.1V2. 27 x 27mm 1mm pitch Pb-free BGA Package3. Absolute maximum power dissipation 1.9 W, typical 1 W4. Operating temperature -40C to 85C without forced air cooling8、数据结构8.1 结构框图8.2 任务消息信源、包处理任务通信包含硬件接口间的握手和固件之间握手 硬件外围固件任务 内部固件任务 内存管理状态机8.3 GPON MACl GPON MAC使得以太网包和TDM承载在PON接口，用GEM的封装模式l 它支持ITU-T G.984.x标准的扩展接口功能l GPON MAC是在PON和包处理器间响应GEM SAR功能，其也支持PON连接间上下T-CONT队列状态机的QoS功能8.3.1 RX Supports rates of 1.244 Gbps and 2.488 Gbps 125s frame synchronization based on physical synchronization field and on the ident field De-Scrambling according to G.984.3 definition using an X7+X6+1 polynomial BIP support in order to measure the link BER Supports PLOAM handling: including ONU-ID filtering, receiving of broadcast PLOAMs,and CRC check Supports Plend data length extraction and check; including CRC Supports payload filtering according to a 32 PORT-ID mapping table. Discards payloads that do not belong to the ONU and IDLE GEM fragments. Supports FEC decoder RS(239,255) Supports AES decryption (counter mode only with 128 bytes of Key) of GEM payload. Configured encryption option is per ONU. Supports GEM header removal and data extraction (GEM SAR) Supports interleaving of 32 RX flows of 32 PORT-IDs Supports one TDM RX flow of up to 20 Mbps on the TDM Interface Supports three discard thresholds: low, high, and very high (data, PLOAM, and OMCI) Supports packet CRC Passes relevant US BW map information to the TX unit Configurable Enable/Disable Includes PM counter block Includes Interrupt block8.3.2 TX Supports rates of 0.622 Gbps or 1.244 Gbps Eight T-CONTS Supports one TDM TX flow at 20 Mbps from the TDM interface to one of the eight payload T-CONTS Additional T-CONT for normal PLOAMS RX unit synchronization Upstream frame generation based on US BW accesses (Overheads + payload) PLOu and PLSu overhead generation based on configured parameters Scrambling according to G.984.3 definition using an X7+X6+1 polynomial BIP generation to measure the link BER Static, urgent, and ranging PLOAM generated by the MIPS Supports GEM header insertion and data segmentation (GEM SAR) Supports packet CRC calculation Supports Idle GEM frame transmission Scheduler to control frame generation and transmission based on US BW records. Supports FEC encoder RS (239,255) Configurable Enable/Disable Automatic disable when RX is disabled8.3.3 下行流GPON下行流，入口GEM帧是指定到具体包放置在适当的RX队列中。基于它们的port-id，这些包被放置在各自握手任务的以态桥队列或者CPU队列。在桥队列中先是在扩展前区分，然后分包送入出口队列。8.3.4 上行流上行以太网包基于优先级被放置在不同的发送队列中，如基于cos，tos或者桥接等，每一个发送队列备连接到一个单播流Tcont。每一个Tcont能维护一个优先级表。每一个Tcont都被指定一个唯一id，以太网包通过多port-id能够合并为独立的id。8.3.5 信源/包处理流程The Cell/Packet Processor handler interfaces with the GPON TX and GPON RXperipherals and the BroadBus.BroadBus physical format adapterTX SM supports:o Round robin filling TX queueso The transport layer of the BraodBus to enable control and data forwarding for the TX queuesRX SM supports:o Push data from GPON MAC RX FIFO to the Cell/Packet Processor SRAMo Manage the RX FIFO in the SRAM by BroadBus messages: Transmit Messages: RX buffer descriptor, Cell/Packet Processor wakeup, and RX payload Receive Message: ACK indicating RX buffer is read by the processor and the buffer is empty8.3.6 GEM Port Interface (TDM)The GEM interface includes a TX clock, TX data, a RX clock, and RX data. The TX clock is generated by the BL2000 and is 19.44 MHz, which is derived directly from the PON clock. The RX clock is generated by an external component, the companion TDM FPGA, and is up to 19.44 MHz.8.3.7 GPON Activation Flow8.4 BPON MAC8.4.1 The BL2000 BPON MAC features include: BPON compliance standardso G.983.1 TC Layer framing and de-churning ITU I.432.1 scrambling Ranging Physical Layer OAM (PLOAM) Full OAM faults and alarmo G.983.2 (OMCI)o G.983.4 (DBA) SR-DBA for enhanced QoS control and peak bandwidth allocation Internal or external queue status reporting on mini-slots Supported data rates:o Downstream: 1.244 Gbps or 622 Mbpso Upstream: 155 Mbps Four level QoS support for upstream traffic Queue managero Eight Traffic Containers (T-Conts)o Flexible assignment of queues for upstream, downstream or CPUo Flexible assignment of queue size and watermark Support for 32 VP/VC group filterso SFU/SBE application is assumedo 32-bit header masko Promiscuous mode Support for up to 32 active AAL5 flows Support for all five types of T-CONTs: types 1, 2, 3, 4 and 5 ATM cell processing with end-to-end OAM per I.610 Derives clock from recovered network clock Enables 8 KHz clock generation from PLOAM SYNC bytes Dedicated connections for In-band management can be directed to CPU (ATMOAM or OMCI)8.4.2 Downstream Flow8.4.3 Received PLOAM Cell Structure8.4.4 Upstream Flow8.4.5 Upstream Cell Handler8.4.6 Loopbacks8.5 以太网MACFor subscriber Ethernet traffic, two Media Access Control (MAC) modules are available. These allow the BL2000 to function in either dual Fast Ethernet mode or single Gigabit Ethernet mode. In dual Fast Ethernet mode, the physical device interface is a dual Reduced Media Independent Interface (RMII). In single Gigabit Ethernet mode, the physical device interface is a Gigabit Media Independent Interface (GMII). The Gigabit MAC is an auto-negotiating 10/100/1000 MAC and may also operate in Media Independent Interface (MII) mode. The Gigabit MAC also includes the MAC Control sublayer, which provides support for Control frames including PAUSE frames.General Ethernet features include: Fast Ethernet 10/100 (IEEE 802.3/802.3u)o Four modes of operation One MII One RMII MII and RMII Dual RMIIo Half and full duplex support Gigabit Ethernet 10/100/1000 (IEEE 802.3ab/802.3z)o GMII MAC Interface Configurable 802.3x flow control CPU flow control Ethernet port by host command to generate Pause frame Programmable watermarks for full/empty FIFO conditions for automaticgeneration of pause frames based on FIFO fill levels. Backpressure issupported for half duplex mode. Configurable enable/disable MDIO interface Support of MTU up to 2 KBytes IEEE 802.1q VLAN tagging VLAN tagging according to 802.1pq VLAN tag to GEM Port mapping for US traffic: VID or TCI Q-in-Q (802.1q VLAN stacking/stuffing) Provides statistic counters to support OMCI and RMON implementation9、MIPS SubsystemThe MIPS Subsystem consists of a MIPS RISC core (CPU), peripherals, and gluelogic. The Subsystem includes a 4KEc MIPS core, 16 KB 2-way Instruction cache, 8 KB 2-way Data cache, Peripheral Bus Interface, Interrupt Controller, UART, I2C, SPI, GPIO, Timers, and register access to all BL2000 units.The CPU has the following main features: High-performance, low-power, 32-bit 4KEc RISC core Single clock multiply operation Memory Management Unit (MMU) I-Cache 16 KB, 2-Way Set Associative D-Cache 8 KB, 2-Way Set Associative, supporting write-back and writethrough operations Cache line locking support Non-blocking pre-fetches MIPS 32 Privileged Resource Architecture Single-stepping of the processor as well as instruction and data virtual address/value breakpoints via EJTAG4.1. MIPS CoreThe MIPS 4KEc core has the following features: Five stage pipeline 32-bit address and data paths MIPS 32 Release 2 instruction set I-Cache 16 KB, 2-Way Set Associative D-Cache 8 KB, 2-Way Set Associative, supporting write-back and writethroughoperations 16-byte cache line size Non-blocking pre-fetches One-clock multiplier (specific to 4KEc core) Programmable Cache Sizeso Individually configurable instruction and data cacheso Direct Mapped, 2-, 3-, or 4-Way Set Associativeo 16-byte cache line sizeo Non-blocking pre-fetches One-clock multiplier (specific to 4KEc core) Programmable Memory Management Unit (specific to 4KEc core)o Sixteen dual-entry Joint TLB (JTLB) with variable page sizeo Four entry Instruction TLB (ITLB)o Four entry Data TLB (DTLB) Multiply/Divide Unito Maximum issue rate of one 32x16 multiply per clocko Maximum issue rate of one 32x32 multiply every other clocko Early-in iterative divide (minimum 11 and maximum 34 clock latency) Power-down mode (triggered by WAIT instruction) EJTAG debug1 EC Buso Works in sequential burst modeo Burst can start from any address and wraps around on burst limito MIPS accesses have a constant burst size of 16 bytes (4 clock cycles)10、信源/包处理10.1、Core Features 32-bit register data width 32-bit wide instructions Thirty two general purpose registers: sixteen 32-bit global registers plus abank of sixteen 32-bit registers for each of the thirty two threads. Dedicated 16-bit Program Counter (PC) register. 16 KByte address space for instructions containing 4K instructions. 48 KByte address space for data memory 256 addresses for I/O data space (used by HW accelerators) Four stage pipeline (Fetch, Decode, Execute, and Write back) Data addressing modes including immediate and register, both direct ordisplacement. Works in big-endian mode Byte, Half-word, Word, and Double word load and store operations. One 32-bit ALU supporting various arithmetic and logic operations. One shift unit (32-bit) supporting arithmetic and logic shifts Special instructions for networking implementations such as extract insert andround robin selection. Two 32-bit registers used as input stage for the execution unit (with bypassoption). 32-bit accumulator register used as output for each part of the Execution unit. Conditional control commands: jump, call subroutine and return. Both JMPand CALL support conditional and unconditional execution. Change of flowcommands support immediate or register branch. A performanceenhancement is the use of delayed slots. An unconditional JMP can executethe opcode immediately following it. Dedicated internal 2-level register based stack. Multi thread. Up to 32 different contexts each with 16 dedicated registers. Thestore of the previous context and the load of the next context are donesimultaneously during the run of the current task. Unless the current contextduration is smaller than 15 commands, there is no penalty when performing acontext switch. Debug support features including two address breakpoints and immediatebreakpoint. Support for low power mode10.2、Firmware Features Supports up to 100 Mbps full duplex sustained Ethernet traffic with 64 bytepackets Classification engine Support for 512 filtering table entries Support for 802.1p wit