verilog设计一四位计数器.doc

FPGA与硬件描述语言实验报告学院：信息技术学院班级：专业：电子信息科学与技术姓名：日期：学号：1. 实验目的1、 熟悉行为级语法；2、 熟悉有限状态机2.1实验内容设计一四位计数器，进行仿真，并检测输出结果；提示：在时钟上升沿，如果复位信号有效，则复位为0,如果复位信号无效，则计数器需要加一。2.2实验内容完成一个序列信号电路检测器，检测信号为10010，当检测到此序列时输出端口输出高电平，其余时间输出低电平。提示：先画出状态转换图或写出状态转换表，根据状态表或者状态图完成代码的设计；编写测试模块对该功能模块进行仿真。要求实验报告包括完整的状态转化图或者转化表。3实验记录序列信号电路检测器：3.1功能块代码module mian (z, x, clock, clear); output z; reg z; input clock, clear; input x; parameter s0 = 3d0, s1 = 3d1, s2 = 3d2, s3 = 3d3, s5 = 3d5, s4 = 3d4; reg 2:0 state; reg 2:0 next_state; always (posedge clock) if(clear) state = s0; else state = next_state; always (state) begin case(state) s0: show = 0; s1: show = 0; s2: show = 0; s3: show = 0; s4: show = 0; s5: show = 1; endcase end always (x or state) begin case(state) s0: if(x = 0) next_state = s0; else next_state = s1; s1: if(x = 0) next_state = s2; else next_state = s1; s2: if(x = 0) next_state = s3; else next_state = s1; s3: if(x = 0) next_state = s0; else next_state = s4; s4: if(x = 0) next_state = s5; else next_state = s1; s5: if(x = 0) next_state = s0; else next_state = s1; endcase endendmodule3.2测试模块代码module stimulus_mv; wire z; reg x; reg clock, clear; mianMVP(z, x, clock, clear); initial begin clock = 0; forever #5 clock = clock; end initial begin clear = 1; repeat(2)(negedge clock); clear = 0; end initial begin #30 x = 1; #10 x = 0; #10 x = 0; #10 x = 1; #10 x = 0; endendmodule 3.3仿真结果：1. 输出：四位计数器3.1功能块代码module counter(out, clock, clear); output out; input clock, clear; reg 3:0 out; always (posedge clock or negedge clear) begin if(clear) out = 4d0; else out = out + 1; endendmodule3.2测试模块代码module counter_stimulus; reg clock, clear; wire 3:0 out; initial $monitor($time, count = %b , clear = %b, out3:0, clear); counter MVP(out, clock, clear); always begin clear = 1b1; #15 clear = 1b0; #200 clear = 1b1; #50 clear = 1b1; end initial begin clock = 1b0; forever #5 c