外文翻译 基于单片机的频率计设计

原文：This design take at MCS-51 monolithic integrated circuit as the core full use hardware source designs one kind of frequency meter, this frequency meter will be measured first that signal enlargement reshaping processing, turns satisfies TTL/which the monolithic integrated circuit I/O mouth accepts the CMOS compatible signal from monolithic integrated circuits T1 input port input direct summation pulse number, the monolithic integrated circuit interior timer fixed time is 1S, by now accumulated the pulse number namely for is measured the signal the frequency. Finally passes through monolithic integrated circuit processing to deliver to the lcd liquid crystal display monitor demonstration.Central Processing Unit DesignsThe CPU is the key component of a digital computer. Its purpose is to decode instruction received from memory and perform transfers, arithmetic, logic, and control operations with data stored in internal registers, memory, or I/O interface units. Externally, the CPU provides one or more buses for transferring instructions, data, and control information to and from components connected to it. In the generic computer at the beginning of chapter 1, the CPU is a part of the processor and is heavily shaded. CPUs, however, may also appear in computers. Small, relatively simple computers called microcontrollers are used in computers and in other digital systems to perform limited or specialized tasks. For example, a microcontroller is present in the keyboard and in the monitor in the generic computer; thus, these components are also shaded. In such microcontrollers, the CPU may be quite different from those discussed in this chapter. The word lengths may be short (say, four or eight bits),the number of registers small, and the instruction sets limited. Performance, relatively speaking, is poor, but adequate for the task. Most important, the cost of these microcontrollers is very low, making their use cost effective.In the following pages, we consider two computer CPUs, one for a complex instruction set computer (CISC) and the other for a reduced instruction set computer (RISC). After a detailed examination of the designs, we compare the performance of the two CPUs and present a brief overview of some methods used to enhance that performance. Finally, we relate the design ideas discussed to general digital system design.1、 The complex instruction set computerThe first design we present is for a complex instruction set computer with a non-pipelined datapath and microprogrammed control unit. We begin by describing the instruction set architecture, including the CPU register set, instruction formats, and addressing modes. The CISC nature of the instruction set architecture is demonstrated by its memory-to-memory access for data manipulation instructions, eight addressing modes, two instruction format lengths, and instructions that require significant sequences of operations for their execution.We design a datapath for implementing the CISC architecture. The datapath is based on the one initially described in Section 7-9 and incorporated into a CPU in section 8-10. modifications are made to the register file, the function unit, and the buses to support the present instruction set architecture.Once the datapath has been specified, a control unit is designed to complete the implementation of the instruction set architecture. The design of the control unit must involve a coordinated definition of both the hardware organization and the microprogram organization. In particular , dividing the microprogram into microroutines, while at the same time designing the sequencer with which they interact, is a key part of the design. Even the instruction fields and opposed are tied to this coordinated effort. Following the definition of the hardware and microcode organizations, we detail essential parts of the microcode and the microroutines for representative operations. Instruction set architectureFigure 10-1 shows the CISC register set accessible to the programmer. All registers have 16 bits. The register file has eight registers, R0 though R7.R0 is a special register that always supplies the value zero when it is used as a source and discards the result when it is used as a destination.In additional to the register file, there is a program counter PC and stack pointer SP. The presence of a stack pointer indicates that a memory stack is a part of the architecture . the final register is the processor status register PSR, which contains information only in its rightmost the five bits; the remainder of the register is assumed to contain zero. The PSR contains the four stored status bit values Z,N,C,and V in positions 3 through 0, respectively. In additional, a stored interrupt enable bit EI appears in position 4. Table 10-1 contains the 42 operations performed by the instructions. Each operation has a mnemonic and a carefully selected oppose. The operations are divided into four groups based on the number of explicit operands and whether the operation is branch. In addition, the status bits affected by the operation are listed.Figure 10-2 gives the instruction formats for the CPU. The generic instruction format has five fields. The first, OPCODE, specifies of the operation. The next two, MODE and S , are used to determine the addresses of the operands. The last two fields, SRC and DST, are the 3-bit source register and destination register address fields, respectively. In addition, there is an optional second word W that appears with some instructions as an operand or an address, but not with others.The first two bits of OPCODE, IR(15:14), determine the number of explicit operands and how the fields of the format are used. When these bits are 00,either no operand is required or the location of the operand is implied by OPCODE. Only the OPCODE field is needed, as shown in figure 2(b).the four rightmost OPCODE bits can specify up to 16 operands or with implied operand addresses.If IR(15:14) is 01, the instruction has one operand and is a data transfer or data manipulation instruction. Since there is an operand, the MODE field specifies the addressing mode for obtaining it. The single address may involve the DST register address in its formation, so the DST field is also present. The S field and SRC field relate to the presence of two operands and so are not used for the typical single operand instructions. but, the shift instructions require a shift amount to indicate how many bits to shift. For maximum flexibility, this shift amount is treated just like a source operand. As a consequence, the SHA and S fields is a full 16-bit operand, but only values 0 through 15 are meaningful. There are sufficient OPCODE bits for 16 instructions with a single operand. Table 10-2 gives the addressing modes specified by the MODE field. The first two bits of MODE specify four different types of addressing: register, immediate, indexed, and relative to the PC. The third bit of MODE specifies whether the address generated by these modes is used as an indirect address. The one exception to this is direct addressing, which is obtained by applying indirection to the immediate type. Otherwise, if the third bit equals 0, indirect addressing does not apply whereas, if it equals 1, indirect addressing does apply. For the register type of instruction, MONE(2:1)=00 and the W word is not needed. Since the operand or address comes from a register. The third column of the table provides register transfer statements for each of the addressing modes for the one-operand instructions.If IR(15:14) is equal to 10, then the instruction has two addresses used for true operands. All fields of the generic instruction, including S and SRC, are used for this case for all instructions. one of addresses, either the source or the destination, uses the addressing modes. If S=0, then the source uses the addressing mode specified by MODE, and the source is a register. If S=1, then the destination uses the addressing mode, and the source is a register. Register transfer descriptions of the resulting addresses are given in the fourth and fifth columns of Table 2. Again, depending on the contents of the MODE field, the second instruction word W, which is an address or an immediate operand, may or may not be present.Instructions with IR(15:14)=11 are branches. Aside form the S field and the SHA field for shifts, the format is the same as for IR(15:14)=01. For all instructions of this type, the destination address (not the operand) becomes the new address placed in the program counter PC. As a consequence, the register mode is invalid for branch instructions.Before proceeding to the next step, which defines the datapath to support the instruction set architecture, we will briefly note the characteristics of the architecture that define it as CISC or RISC. Most of the operations given in Chapter 9 are included in the instruction set. A number of operations that do not appear are redundant. The same actions can be achieved by using proper addressing modes with instructions that do appear. For example, LD, ST, IN, and OUT can all be achieved by using MOVE instructions in a memory-mapped structure. By looking at the formats for the instructions, we find that most of the instructions can operate directly on operate directly on operands from memory. There are eight addressing modes and two different lengths of instruction formats. In addition, some of the instructions perform complex operations which can be viewed as operations that are likely to take more than one clock cycle for the execution step. These characteristics clearly identify this as a CISC architecture.Datapath organizationRather than beginning from scratch, we will reuse the non-pipelined datapath employed with the microprogrammed control in section 8-10, with modifications. That datapath was shown in section 8-10, and the new, modified datapath based on it is given in Figure 10-6. we treat each modification in turn, beginning with the register file.In section 8-10, register R8 was used as a temporary storage location. In the new microprogrammed architecture, there are complex instructions spanning many clock cycles and performing complicated operations. Thus, more temporary storage is needed for use by the microprograms. To meet this need, we expand the register file from 9 registers to 16. the first 8 registers, R0 through R7, are visible to the computer programmer. The second 8 registers, R8 though R15 , are used as temporary storage for the microprogram operands and are hidden from the programmer. Figure 10-3 provides a map of the expanded register file with the temporary registers shaded. As indicated previously, register R0 supplies the constant 0. registers R1 through R7 are available to the programmer for use, and registers R8 through R15 provide general temporary storage for use by microprograms, the last four registers, R12 though R15, have special uses: to keep the microcode simple, standard locations are essential for storing the operands and addresses used by execution microcode for most instructions. thus ,R12 is the location for the source address(SA), R13 for the source data (SD), R14 for the destination address(DA), and R15 for the destination data(DD).We cannot access the eight temporary registers based on the 3-bit register address available in the instruction. To deal with this problem, we provide, first, 4-bit register address from the microinstruction, and second, a microinstruction bit to choose between these addresses and those from the instruction. In addition, the flexibility to allow the register addressed by DST to be a source and by SRC to be a destination is needed to permit results of operations to be placed directly in memory. To accomplish these goals, we modify the register file by adding the logic shown in Figure 10-4(a). the instruction set architecture uses two addresses, one for a source a operand and the other for the other source as well as the destination. The register file uses the B address for a source, and the A and D addresses on the file are connected together, giving the same address for the other source and the destination. Although this reduction from three to two addresses is not essential at the mincroinstruction level, it decrease the number of bits needed for register addresses in the microinstruction and matches the use of the register fields in the instruction formats.A quad 2-to-1 multiplexer is attached to each of the two address inputs to the register file, to select between an address from the microinstruction and an address from the instruction. There is a 5-bit field in the microinstruction for the combined destination and source address DSA, in addition to a 5-bit field for the B address SB. The first bit of each of the these fields selects between the register file address in the microinstruction(0) and the register file address in the instruction(1). If an instruction address is selected, whether it is DST or SRC is determined by an additional quad 2-to-1 multiplexer. This multiplexer is controlled by the second bit of the DSA or SB fields, depending on which of them has 1 in the first bit in any microinstruction, thereby ensuring that the proper second bit is used to determine the register address. A 0 is appended to the left of the 3-bit fields DST and SRC to cause them to address R0 through R7. the addition to the first bit, which selects the address source, the addresses from the microinstruction contain four bits so that all 16 registers can be reached. The final change to the register file is to replace the storage elements for R0 in the file with open circuits on the lines that were their inputs and with constant zero valves on the lines that were their outputs. A symbol for the resulting register file is show in Figure 10-4(b).We find that, based on the eight shift instructions provided, the shifter from section 8-10, needs to be modified. The modifications involve the end bits of the shift logic. For logical shifts, a 0 is inserted, as before. For the right arithmetic shift, she sign bit is the incoming bit, and for the left arithmetic shift, 0 is the incoming bit. Rotates require that the bit from the opposite end of the shifter be fed around. Finally, rotates with carry require that the carry flip-flop output be provide as an input on both ends of the shifter.2.SummaryIn this paperwe examined two CPU designs: the CISC and RISC.The CISC control unit includes a stack pointer in addition to the program counterControl microprograms reside in ROMand a combination of a multiplexer and a ROM provides fast instruction decodingThe control unit also has extensiveump and conditional branching capabilities，including one level of microsubroutinesThe microprogram for the control is modularized to permit many microsubroutines to be shared in implementing the microprogram for the instructionsThe RISC control unit is pipelined and has special hardware added to deal with branches. Pipelined CPUs have both data and control hazard problemsWe examined one of each type of hazard，as well as software and hardware solutions for eachAfter discussing CISC and RISC performance，we touched on some advanced concepts, including parallel execution units, a combination of microprogrammed control with a pipeline，superpipelined CPUs, superscalar CPUs，and predictive and speculative techniques for high-performanceFinally, we related the design techniques in this paper to more general digital system design原文翻译：本设计以MCS-51单片机为核心充分利用硬件资源设计的一种频率计，该频率计首先将被测信号放大整形处理，变成满足单片机I/O口接受的TTL/ CMOS 兼容信号从单片机的T1输入口输入直接累加脉冲数，将单片机内部定时器定时为1S，这时累加的脉冲数即为被测信号的频率。最后经单片机处理送至lcd液晶显示屏显示中央处理器设计CPU(中央处理单元)是数字计算机的重要组成部分, 其目的是对从内存中接收的指令进行译码，同时对存储于内部寄存器、存储器或输入输出接口单元的数据执行传输、算术运算、逻辑运算以及控制操作。在外部，CPU为转换指令数据和控制信息提供一个或多个总线并从组件连接到它。在通用计算机开始的第一章，CPU作为处理器的一部分被屏蔽了。但是CPU有可能出现在很多电脑之间，小，相对简单的所谓微控制器的计算机被用在电脑和其他数字化系统中，以执行限制或专门任务。例如，一个微控制器出现在普通电脑的键盘和检测器中，但是这些组件也被屏蔽。在这种微控制器中，与我们在这一章中所讨论的CPU可能十分不同。字长也许更短，（或者说4或8个字节），编制数量少，指令集有限。相对而言，性能差，但对完成任务来说足够了。最重要的是它的微控制器的成本很低，符合成本效益。在接下去的几页里，我考虑的是两个计算机的CPU，一个是一个复杂指令集计算机（ CISC），另一个是精简指令集计算机（RISC）。在详细的设计检查之后，我们比较了两个CPU的性能，并提交了用来提高性能的一些方法的简要概述。最后，我们讨论了关于一般数字系统设计的设计思路。1复杂指令集计算机我们提交的第一个设计就是为一个带有非流水线数据路径和微程序的控制单元的复杂指令集计算机而设计的。我们以介绍指令集构架为开端，它包括CPU的注册设置，教学形式，和处理方式。复杂指令集计算机（ CISC）的指令集构架的性质是通过它的内存到内存进行数据存取操作指示8个处理模式，两长指令格式和指令集，来为它们的执行获得重要的运行序列。我们为实施复杂指令集计算机（ CISC）构架而设计一个数据路径。这个数据路径是基于最初描述的7-9节里，并纳入了8-10节里的CPU中。对登记档案，功能单元以及总线进行修改来支持现有的指令集构架。一旦数据路径被明确，被设计的一个控制单元就去完成指令集构架的执行。控制单元的设计必须涉及硬件组织和微程序组织的一个协调的定义。特别是把微程序分成微线路，然而同时也设计了它们相互影响的音序器，这是设计的关键部分。即使是指令集领域和有联系的同代码的这种协调一致的努力。以下是硬件和微代码组织的定义，我们详细描述的是为运行代表的微型代码个微型线路的基本部分。1.1指令集构架图1显示了程序员获得的一套复杂指令集计算机（ CISC）的寄存器。所有的注册有16位。这个注册文件有8个寄存器，从R0到R7。R0是一个寄存器，当它被作为目的来使用，作为来源和抛弃的结果来使用时她总是提供零价值。除了注册文件，还有一个程序计数器pc和堆栈指针SP。堆栈指针的出现的情况表明内存堆栈是构架的一部分。最后登记的是处理器状态寄存器PSR，它包括最右边的五个位的信息；剩下的都被假定包含0.该处理器状态寄存器包含四个存储状态位值Z,N,C,和V，他们分别位于0-3之间。另外，一个存储中断使得EI处在4的位置上。图1包含了42个通过指令集进行的操作。每个操作都一个记忆和精心挑选的同位代码。根据一些明确的操作和是否分开操作，将这些操作分成4组。另外，这些状态位受到被列开的操作的影响。 图1图2给出了CPU的指令格式。通用指令格式的有五个领域。首先，OPCODE是指定的操作。接下去的两个是MODE 和 S，是被用来确定运算的地址。最后两个领域是SRC和DST，分别是3位的来源登记和目的地登记领域。此外，还有一个可选的第二个字母W，随着一些作为一个操作或一个地址的指示而出现的，而不是随着其他出现的。图2OPCODE的前两位，IR（15：14），确定了一些明确的操作和格式领域的如何使用。当这些位是00时 ，要么是没有被要求的操作要么是被OPCODE隐含的操作的位置。正如图2(b)显示的，只有OPCODE领域的是需要的。右边的4个OPCODE位可以指定多达16个操作或带有暗示的操作地址。如果IR是（15：14）是01，指令有一个操作，且是数据传输或数据操作指令。因为有了一个操作，MODE领域就会为获得它而指定处理方式。单处理可能会涉及DST格式里的注册地址，所以DST领域也会被引出。S领域和SRC领域涉及到两个运算的同时出现，因此不被用于典型的单一的操作指示。但是，切换指令要求有一个切换数额来只是到底切换多少位。为获得最大的灵活性，这个切换数额是只针对像来源运算一样的的运算。因此，SAH领域和S领域是一个完整的16位运算，但它们的值只有0-15是有意义的。对带有单一运算的16位指令来说有足够的OPCODE位。图2给出了指定通过MODE领域的处理方式。MODE的前两位指定了4中不同的处理类型：注册、立即、索引以及相关的程序计数器PC。MODE的第三位明确是否地址是通过这些被用作间接处理的模式而形成。一个例外就是直接处理，它是通过运用间接立即类型而获得的。否则，如果第三位等于0的，间接处理就不适用，而如果等于1 ，间接处理就适用。对指令的注册类型来说，MONE(2:1)=00和这个W字母是不需要的。因为运算或处理是来自注