双口RAM.doc

双口1模块功能： 双口RAM模块主要采用IDT7132等器件，它是一种特殊的数据存储芯片，它既可以用于单片机存储大容量的数据，也可以以双口RAM为共享存储器来实现两个处理器之间的通信和数据传输。双口RAM的优点是提供了两条完全独立的端口，每个端口都有完整的地址、数据和控制总线，允许两个CPU对双端口存储器的同一单元进行同时存取；具有两套完全独立的终端逻辑来实现两个CPU之间的握手控制信号；具有两套独立的“忙”逻辑，保证两个CPU同时对同一单元进行读/写操作的正确性。对于单个CPU而言，双口RAM同普通RAM没有什么明显的区别。 本模块原理图见图。图 3主要器件： (1)IDT7132：(a)器件功能：IDT7132是高速2k*8端口静态RAM，可提供 图2.1.3 IDT7132引脚图两个拥有独立的控制总线、地址总线和I/O总线端口，允许CPU独立访问内部的任何存储单元。当/CE 引脚出现下降沿时，选中DPRAM即可通过控制OE 或R/W来访问内部存储单元。(b) 器件引脚：IDT7132的引脚图如图2所示。/CE、/CER：（左、右）片选控制信号。R/WL、R/WR：（左、右）读写控制信号。/OEL、/OER：（左、右）使能控制信号。/BUSYL、/BUSYR：（左、右）繁忙查询控制信号。A0LA9L、A0RA9R：（左、右）地址总线。I/O0LI/O7L、I/O0RI/O7R：（左、右）输入/ 输出总线。 VCC：电源。(c) 工作原理：IDT7132的工作时序如图3所示。它与RAM的读写时序非常类似。当CPU选中DPRAM时/CE引脚出现下降沿，当控制线/OE为高且R/W 为低时，CPU对内部存储单元进行写操作；而当控制线OE为低且R/W为高时，CPU对内部存储单元进行读操作。当外部CPU通过两个端口对双口RAM内部的同一个存储单元进行操作时，系统将出现竞 图 2争。这种竞争一般有如下两种模式：（1） 如果两个端口的总线访问地址相同，并先于片选信号/CE有效，则片内逻辑将在CEL与CER之间发生竞争。（2） 如果两个端口的片选信号CE在地址信号有效之前变低，则片内控制逻辑将在地址信号到达时发生竞争。为避免因竞争而导致的通讯失败，设计者提出了意下三种常见的解决方案。（1） 设置标志位：在开辟数据通讯区的同时，可通过软件方法在某个固定 的存储单元设立标志位。这种方法要求 两端CPU每次访问双 图 3口RAM之前，必须查询、测试和设置标志位，然后再根据标志位的状态决定是否可以访问数据区；有的双口RAM本身就具有专用的一个或多个硬件标志所存器和专门的测试和设置指令，可直接对标志位进行读/写操作。这种方法通常用在多个处理器共享一个存储器块时。为了保证通讯数据的完整性，在采用这种方法时往往要求每个处理器能对该存储器块进行互斥的存取（2） 软件查询BUSY引脚状态：双口RAM必须具有解决两个处理器同时访问同一单元的竞争仲裁逻辑功能。当双方访问地址发生冲突时，竞争仲裁逻辑可用来决定哪个端口访问有效，同时取消无效端口的访问操作，并将禁止端口的BUSY信号之为低电平。因此BUSY信号可作为处理器等待逻辑的输入之一，即当BUSY为低电平时，让处理器进入等待状态。每次访问双口RAM时，CPU检查BUSY状态已判断是否发生竞争，只有BUSY为高时，对双口RAM的操作才有效。（3） 利用硬件解决竞争：将BUSY信号引入CPU的READY引脚可在发生竞争时使BUSY为低，从而使CPU内部总线时序根据READY引脚状态自动插入WAIT信号并展宽总线，以达到分时访问的木的。另外，在使用BUSY信号时必须首先将此信号接上拉电阻，其次应在BUSY信号有效期间使处理器保持读写操作以及相应的地址和数据，但是需要说明的是，在BUSY信号变高之前，这种情况下的所有操作都是无效的，图4所示是发生竞争时的时序图。 图 4(2)74HC573：(a)器件功能：74HC573是一个8D触发器。(b) 器件引脚：74HC573的引脚图如图5所示，器件的内部电路如图6所示。 图 5 图 6/OE：输出控制线，当OE为高电平时，输出为高阻态，当OE为低电平时，输出端为触发器中的数据。LE：控制器的数据保持功能使能线，当LE为高电平时，触发起位保持作用，这时触发器存储了LE上升沿时触发器输入端的状态。D0D7：数据输入端。Q0Q7：数据输出端。GND：接地。VCC：接电源。(c)工作原理：74HC573的功能表如图7所示。 图 7(3)74LS245：(a)器件功能：74LS245是双向三态缓冲器。(b) 器件引脚：74 LS245的引脚图如图8所示，器件的内部电路如图9所示。 图 8 图 9DIR：数据传输方向选择端。本模块中数据从端向端传输。/G：输出允许信号端。A1 A8：I/O端口。B1B8：I/O端口。VCC：接电源。GND：接地。(c)工作原理：74 LS245的功能表如图10所示。 图 103.接口说明双口RAM 模块的PCB图如图11所示，实物图如图12所示。 图 11 图 12实物图中单片机模块上的外围接口说明如下：P0A1 A8)：地址数据复用总线。左面端口的地址和数据都由此端口输入，通过双向三态缓冲器74LS245和8D触发器74HC573分别送至IDT7132的地址端口和数据端口。P1/CE、R/WL、/OEL、A10、A9、A8、/BUSYL、GND)P2(0RA10R、I/O0RI/O7R、/OER、R/WR、/CER、/BUSYR)以上各端口的具体用途见前面IDT7132的引脚的引脚说明。4.典型程序通过键盘向双口RAM写数据并通过液晶显示。#include #include#define uchar unsigned char#define uint unsigned int#define lcd_bus P0#define key_bus P2sbit ce=P34;sbit rs=P15;sbit rw=P13;sbit e =P11;sbit en=P24;uchar xdata sin12048=0; uchar temp=0;uchar code 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