altera fpga的设计流程.ppt

1,alterafpga的设计流程,贺光辉清华大学电子工程系,2,目标,掌握fpga的标准设计流程和工具用modelsim进行功能级仿真并诊断rtlcode用quartusii做设计综合和布局布线用fpgamega-functions做设计返标sdf并运行门级的仿真掌握fpga的时序约束了解fpga的设计原则,3,提纲,fpga概要fpga的设计流程用modelsim进行仿真和调试用quartusii进行时序分析、综合等fir滤波器的设计实例,4,fpga概要,5,fpga的优点,集成度高，可以替代多至几千块通用ic芯片极大减小电路的面积，降低功耗，提高可靠性具有完善先进的开发工具提供语言、图形等设计方法，十分灵活通过仿真工具来验证设计的正确性可以反复地擦除、编程，方便设计的修改和升级灵活地定义管脚功能，减轻设计工作量，缩短系统开发时间布局布线容易，设计过程相当于只有asic设计的前端研发费用低不需要投片费用,6,fpga的应用前景,通信、控制、数据计算等领域得到了广泛的应用减少电子系统的开发风险和开发成本缩短上市时间（timetomarket）通过在系统编程、远程在线重构等技术降低维护升级成本系统的原型实现asic的原型验证,asic常用fpga进行原型机验证,7,cpld与fpga的区别,8,cpld还是fpga？,复杂组合逻辑：cpldpld分解组合逻辑的功能很强，一个宏单元就可以分解十几个甚至2030多个组合逻辑输入复杂时序逻辑：fpgafpga芯片中包含的lut和触发器的数量非常多，往往都是成千上万,9,推荐书籍,verilogverilog数字系统设计教程夏宇闻北京航天航空大学出版社硬件描述语言verilog刘明业等译清华大学出版社fpga基于fpga的嵌入式系统设计任爱锋西安电子科技大学出版社基于fpga的系统设计（英文版）waynewolf机械工业出版社ic设计reusemethodologymanualforsystem-on-a-chipdesigns3rded.michaelkeating,pierrebricaud.片上系统:可重用设计方法学沈戈,等译电子工业出版社,2004writingtestbenches:functionalverificationofhdlmodels/janickbergeronboston:kluweracademic,c2000,10,推荐文章,http:/www.sunburst-nonblockingassignmentsinverilogsynthesis,codingstylesthatkill!,11,fpga的设计流程,12,目标,完成本单元的学习后你将会列出fpga设计过程的步骤（以altera的fpga为设计例子）用缺省的软件选项来实现一个fpga的设计quatursiimodelsim,13,fpga的设计流程,fpga的设计流程用modelsim进行仿真用quartusii进行综合和时序分析用quartusii进行布局布线、调试和下载,14,fpga设计流程,综合-translatedesignintodevicespecificprimitives-optimizationtomeetrequiredarea如果没有使用,sdf用于顶级,50,用modelsim作时序仿真(总结),基本仿真步骤：建立库编译altera器件库3映射库到物理目录4编译综合后网表5加入sdf文件4启动仿真器5执行仿真,#scriptformodelsimposttimingsimulationofalteracyclonedevice#bywayne#setyourpcenvironmentsetmodelsim_homed:/edatools/modeltech_6.1dsetquartus_homed:/quartus51#buildworklibvlibwork#addcyclonedevicelibanditssimmodelsvlog-reportprogress300-workcyclone$quartus_home/eda/sim_lib/cyclone_atoms.v,程序接下页,51,vmapcyclonework#postsimulationinmodelsimforalteradevicessetdesign_namechip_topsethome./impvlog./src/tb_top.vvlog./imp/simulation/modelsim/$design_name.vovsim-sdftyp/tb_top/uut=chip_top_v.sdo-tpswork.tb_topdowave.dorun500us,程序接上页,52,用quartusii进行综合、时序分析和布局布线,53,设计流程,createanewquartusiiprojectcompileadesignintoanfpgalocateresultingcompilationinformationassigndesignconstraints(timingworstfmaxislistedonthetop,source,destinationregisters&associatedfmaxvalues,clocksetup(fmax)tables,74,fmaxanalysisdetails,datadelay(b),sourceregisterclockdelay(c),setuptime(tsu),b,c,tco,tsu,e,clockperiod,destinationregisterclockdelay(e),clocktooutput(tco),1,0.384ns+7.445ns+0.180ns-0.000ns,=124.86mhz,messageswindow(systemtab)inquartusii,75,i/oassignments:tsu,tco,76,timingassignments,whatcanbetaggedwithatimingassignments?registers(all)clockpins(all)inputpins(tsu,th)outputpins(tco)bidirectionalpins(all),77,timingsettings,easywaytoentertimingassignmentsconsolidatesalltimingassignmentsinonemenuindividualclocksettingsoroverallcircuitfrequencydefaultsystemtimingtsuthtcotpddefaultexternalinput/outputdelaysenable/disabletiminganalysisduringcompilationtimingdrivencompilation,78,reportingtimingresults,timinginformationispartofthecompilationreportsummarytiminganalysesfmax(notincl.delaysto/frompins)orfmax(incl.delaysto/frompins)register-to-registertabletsu(inputsetuptimes)th(inputholdtimes)tco(clocktooutdelays)tpd(pintopindelays)alltimingresultsarereportedhere,79,i/o建立时间和保持时间,clockdelay,tsuth,datadelay,tsu=datadelay-clockdelay+intrinsictsu,intrinsictsu&hold,th=clockdelay-datadelay+intrinsicth,80,i/oclock-to-outputanalysis(tco),datadelay,tco,clockdelay,clockdelay+intrinsictco+datadelay=tco,intrinsictco,81,timeslack,slack=期望数据到达时间数据实际到达时间,slack为正，表示数据提前到达，此时组合逻辑延迟满足条件，register有足够的建立时间；slack为负，表示数据比预期的时间晚到达，此时显然不满足register的建立时间，不满足约束；,82,slackequations(setup),slack=largestrequiredtime-longestactualtimerequiredtime=clocksetup-tco-tsu+(clk-clk)actualtime=datadelay,launchedge,clk,clk,setuplatchedge,clocksetup*,clk,tco,tsu,combinatoriallogic,clk,register1,register2,datadelay,83,slackequations(hold),launchedge,clk,holdlatchedge,clockhold*,clk,tco,th,combinatoriallogic,clk,register1,register2,datadelay,slack=shortestactualtime-smallestrequiredtimeactualtime=datadelayrequiredtime=clockhold-tco+th+(clk-clk),clk,84,in,out,clk,reg1,reg2,clk,clk,clk,slack=p2prequiredp2pdelay,p2p,p2prequired=setuprelationship+clockskewtco-tsu,setuprelationship=latchedgelaunchedge,clockskew=clkclk,launch,latch,simpleregistertoregister示例,85,in,out,clk,reg1,reg2,clk,slack=p2prequiredp2pdelay,p2prequired=setuprelationship+clockskewtcotsu,setuprelationship=latchedgelaunchedge=5.00.0=5.0,clockskew=clkclk,2.266,0.11,0.082,tco,tsu,0.082,0.11,=2.521-2.993,=5.0+(-0.472)0.110.082,=4.3362.266,=-0.472,=4.336,tco,tsu,=2.07,2.993,2.521,simpleregistertoregister示例（con）,86,inputminimumdelay,minimumdelayfromexternaldevicetoalterai/orepresentsexternaldevicetco+pcbdelay+pcbclockskewconstrainsregisteredinputpath(th),a,tco,th,alteradevice,externaldevice,pcbdelay,thainputminimumdelay,inputminimumdelay,tha,clk,clk,87,outputmaximumdelay,maximumdelayfromalterai/otoexternaldevicerepresentsexternaldevicetsu+pcbdelay+pcbclockskewconstrainsregisteredoutputpath(max.tco),b,tco,tsu,alteradevice,externaldevice,pcbdelay,tcobtclk-outputmaximumdelay,tco,outputmaximumdelay,clk,clk,88,outputminimumdelay,minimumdelayfromalterai/otoexternaldevicerepresentsexternaldeviceth-pcbboarddelayconstrainsregisteredoutputpath(min.tco),b,tco,th,alteradevice,externaldevice,boarddelay,tcoboutputminimumdelay,tco,outputmaximumdelay,clk,clk,89,exampleinputmaximumdelay,notice:inputpind(6)&d(3)timinginformationisincludedwithclocksetup(fmax)analysisinputdelayhasbeenaddedtolistpathcalculation,inputmaximumdelay(d)=4ns,90,compilinginquartus,91,compilinginquartus(start),92,compilinginquartus,93,done!,94,downloadbitfile,95,downloadbitfileintofpga,96,alterafpga配置列表,97,debugwithsignaltapii,98,quartusii嵌入式逻辑分析仪特点,99,fir滤波器设计实例,100,一个综合的例子,fir滤波器的设计modelsim的使用quartusii的使用宏功能模块的使用仿真、综合等过程及报告的查看,101,设计要求,设计一个14阶fir滤波器，已给出滤波器系数，要求用verilog/vhdl实现该滤波器，并且选用altera的stratix或stratixii器件。要求充分利用alterastratix/stratixii的器件的dspblock资源。要求每一级都一级流水线(pipeline)。能够利用altera的megafunction。能够在modelsim下进行仿真。选用ep2s60f484c3器件。fmax达到270mhz以上。,102,设计难点,难点在于要达到270mhz以上的频率通过插入流水线可以达到要求为了不过分的增加流水线寄存器的数量，需要对fir滤波器的结构进行精心设计,103,直接形式结构,关键路径是1个乘法器和2个加法器,流水线割集插入流水线寄存器，这样得到的关键路径是1个乘法和1个加法,104,数据广播结构,关键路径是1个乘法器和1个加法器,流水线割集插入流水线寄存器，关键路径是1个乘法,105,设计方案选择,106,fir滤波器的结构,107,模块划分,乘法器模块：直接用altera的dspblocklpm_mult进行例化,加法器模块：直接用altera的dspblocklpm_add_sub进行例化,顶层模块：将乘法器和加法器连接成数据广播结构的fir滤波器,108,dspblocksforcomplexarithmeticapplications,wirelessfiltering&compressionencryptionsignalprocessingconsumerimageprocessingaudioprocessingcompressiondatacombarrelshiftingqosalgorithms,+,optionalpipelining,outputregisters,outputmux,+-s,+-s,inputregisters,109,stratixiidspblocks,up96dspblockseachconfiguredfor(8)9