[synopsys]SVTBOne Day Quick Start.ppt

introductiontosystemverilogfortestbench,onedayquickstart,robertfreemanchrisspearcae,testbenchacwwas,2/24/05,agenda,introductiongettingstartedlanguagebasicsconnectingtoyourdutdriving,sampling,synchronizingoopbasicsrandomizationspawningprocessesfunctionalcoveragetestbenchmethodology,2/24/05,bytheendofthisclass,youshouldbeableto:,lectureobjectives,developselfcheckingtestbenchesusingsystemverilog3.1ahowtoconnectyourdesigntoasvtestbenchhowtoperformrandomconstrainedtestinghowtotakeadvantageofpowerfulconcurrencyhowtoimplementfunctionalcoveragehowtoincorporatemethodologyconcepts,2/24/05,basedonsystemverilog3.1astandarddetailedinlanguagereferencemanualverificationspecificlanguagefeaturessystemverilogassertions(sva)coveragebestinclassconstraintsolverthispresentationisbasedonconstructspresentlyimplementedinvcs2005.06alpha,systemverilogforverification,introduction,2/24/05,verificationenvironmentdefinitions,dut,driver,transactor,monitor,suppliesdatatothedut,observesdatafromdut,executestransactions,identifiestransactions,checkscorrectness,createsstimulus,testbench,assertions,test,checker,selfcheck,verificationenvironment,2/24/05,agenda,introductiongettingstartedlanguagebasicsconnectingtoyourdutdriving,sampling,synchronizingoopbasicsrandomizationspawningprocessesfunctionalcoveragetestbenchmethodology,2/24/05,whatarewegoingtodiscuss?,gettingstarted,setupbasicssv3.1atestbenchverificationflowcompilingandrunninginvcsdebuggingdocumentationandsupporttheprogramblock,2/24/05,gettingstarted,placethefollowinginyour.cshrcsetenvvcs_homesetenvsnpslmd_license_fileporthost:porthost.setpath=($vcs_home/bin$path),setupbasics,2/24/05,gettingstarted,svtestbenchflow,hdl,compilation,simulation,compile,hdlsimulator,hdldut.v,singleunixprocess,svtestbenchprogramtest.v,2/24/05,compile:vcs+svtbtest.vdut.v+svtbenablesvtestbenchconstructs(willbesveriloginfinalrelease)-debugenabledebugexceptlinestepping-debug_allenabledebugincludinglinesteppingrun:simv+user_tb_runtime_options-llogfilecreatelogfile-uclirunwithnewdebugger(seenextpage)-icmd.keyexecuteuclicommands-kkeyfilerenamekeyfile,gettingstarted,compilingandrunningwithvcs,seethevcsuserguideforalloptions,2/24/05,gettingstarteddebugging,ucli:unifiedcommandlineinterfacemakesdebugeasyandconvenientcommonlook-and-feelenvironmentacrosssnpstoolsruntimefeaturesucliacceptsbothvhdlandverilogpathnamestclscriptingfriendlylogscommandsforreplay,commandlinedebugger,magellanmixedhdlvhdlntbvera,systemverilogdesignsystemverilogassertionssystemverilogtestbenchcoveragecbug/systemc,2/24/05,gettingstarted-debugging,callcalltasks,functions,oruserplichangedepositavalueonasignalorvariablecontinuecontinueuntilthenextbreakpoint(assertions,userinterrupts,simulationend,$stop)editinvokesaspecifiededitorenvdisplaysanenvironmentarrayorqueryanarrayelementfinishfinishes/endsrunningaprocess/simulation,forcevariable=valueforcesavalueonavariablegetvariabledisplaysthecurrentvalueofavariablehelpdisplaysinfoonallorspecificcommandslistingdisplaynlinesofsourcecodearoundcurrentlinenextstepovertasks/clockingblock/classdeclarations/tasks/functions/variablesinitialbegin;endendprogram,gettingstarted-sv3.1aprogramblock,sv3.1aprogramblockstructure,partofdesignhierarchy,likemodule,butalwaysaleaf,2/24/05,gettingstarted-sv3.1aprogramblock,benefits:encapsulatesthetestbenchseparatesthetestbenchfromthedutprovidesanentrypointforexecutioncreatesascopetoencapsulateprogram-widedatafunctionality:canbeinstantiatedinanyhierarchicallocationtypicallyatthetoplevelportscanbeconnectedinthesamemannerasanyothermoduleexecutesinthesvreactiveregion,programblock,2/24/05,gettingstartedtestbenchtiming,thetestbench(program)runsseparatelyfromdesign(module)triggeredbyclocksamplesjustbeforeclockedge,drivesjustafterclock,systemverilogtestbenchinsimulation,clock,sampleinputs,driveoutputs,design,testbench,2/24/05,agenda,introductiongettingstartedlanguagebasicsconnectingtoyourdutdriving,sampling,synchronizingoopbasicsrandomizationspawningprocessesfunctionalcoveragetestbenchmethodology,2/24/05,svlanguagebasics,systemverilog3.0and3.1basicsdatatypesarrayssubroutinesassumeyoualreadyknowmostverilog-1995and2001constructs,whatarewegoingtodiscuss?,2/24/05,basicsystemverilogdatatypes,regr;/4-stateverilog-2001logicw;/4-valuedlogic,seebelowbitb;/2-statebit0or1integeri;/4-state,32-bits,signedverilog-2001byteb8;/8bitsignedintegerinti;/2-state,32-bitsignedintegershortints;/2-state,16-bitsignedintegerlongintl;/2-state,64-bitsignedinteger,explicit2-statevariablesallowcompileroptimizationstoimproveperformance,sv3.0datatypes,logicishassingledriver(proceduralassignmentsoracontinuousassignment),canreplaceregandsingledriverwire.(equivalentto“std_ulogic”invhdl),bitsubsallowed,2/24/05,svlanguagebasics,enum-enumeratedtypeexplicitlytypedprovidesforcompiletimeerrorchecking,sv3.0datatypes,/declaredatatypetypedefenuminit,decode,idlefsmstate;fsmstatepstate,nstate;/declarevariablescase(pstate)idle:nstate=init;/dataassignmentinit:nstate=decode;default:nstate=idle;endcase,2/24/05,svlanguagebasics,othersevents,semaphores,mailboxes,stringsandmore!otherconstructs,suchas:timerealvoiduserdefineddatatypesuserdefineddatatypessuchastypedefandclass,sv3.1adatatypes,typedefbit1:5bsix;/definenewtypebsixmy_var;,2/24/05,svlanguagebasics,packedandunpackedarrays,bit7:0b;,bitc7:0;,0,1,2,3,4,5,6,7,0,unused,bit31:0d3:0;,31:0,31:0,31:0,31:0,unused,1,unused,2,unused,3,unused,4,unused,5,unused,6,unused,7,unused,2/24/05,svlanguagebasics,fixedsizearraysalldatatypescanbedeclaredasarraysmultipledimensionssupported,arrays,bit7:0c1;/packedarrayofbitslogicu7:0;/unpackedarrayintarray832;/sameas:intarray0:70:31;bit3:07:0joe1:10;/10entriesof4bytes,/packedinto32bitsbit1:61:5foo41:81:7;/1:5variesmostrapidly,/followedby1:6,1:7and1:8typedefbit1:5bsix;/definenewtypebsix1:10foo5;/1to5variesmostrapidlytypedefbsixmemsix0:3;/arrayof4bsixelementsmemsixbar0:7;/arrayof8mem_typeelements,2/24/05,svlanguagebasics,dynamicarrays-fastsimilartoafixedsizearray,butsizegivenatruntimesingledimensiononly,neverpacked,arrays,inta=new5,/startwith5elementsb,j;for(j=0;ja.size();j+)/initializeaj=j;b=a;/copyadynamicarrayb0=5;$display(a0,b0);/seebothvaluesa=new100;/allocate100newintegers/oldvalueslosta.delete();/deleteallelements,2/24/05,svlanguagebasics,queuesflexiblevariablesizearraywithautomaticsizingmanysearching,sorting,andinsertionmethods(seelrm)constanttimeforread,write,andinsertatfrontintj=2,b$=4,5;q.insert(2,j);/0,1,2,3,6insertbefores2q.insert(4,b);/0,1,2,3,4,5,6insertwholequeueq.delete(1);/0,2,3,4,5,6deleteelement#1q.push_front(7);/7,0,2,3,4,5,6insertatfrontj=q.pop_back();/7,0,2,3,4,5j=6q.push_back(8);/7,0,2,3,4,5,8insertatbackj=q.pop_front();/0,2,3,4,5,8j=7for(j=0;jvcs+svtbtest.varb.vtop.v-debugsimv,alwaysusedebugswitchtocatchnullobjectaccess,2/24/05,agenda,introductiongettingstartedlanguagebasicsconnectingtoyourdutdriving,sampling,synchronizingoopbasicsrandomizationspawningprocessesfunctionalcoveragetestbenchmethodology,2/24/05,driving,sampling,synchronizing,signalaccessfromclockingblocksynchronizationsampledrive,whatarewegoingtodiscuss?,2/24/05,usingtheclockingblock,clockingblocksignalsarereferencedbypre-pendingtheclockingnametothesignal:value=cbarb.grant;/samplecbarb.request=1;/drive,signalaccess,alldrivesmustuseclockingdriveassignment,clockingcbarb(posedgeclk);defaultinput#1output#0;/#1stepoutputreset=reset_p;outputrequest=request_p;inputgrant=grant_p;endclocking,2/24/05,gettingstartedtestbenchtiming,thetestbench(program)runsseparatelyfromdesign(module)clockingblocktriggeredbyclocksamplesjustbeforeclockedge,drivesjustafterclock,systemverilogtestbenchinsimulation,clock,sampleinputs,driveoutputs,design,testbench,2/24/05,gettingstarted-sv3.1areactiveregion,eachtimestepisdividedinto5majorregions(pluspli)preponesamplesignalsbeforeanychanges(#1step)activedesignsimulation(module),includingnbaobservedassertionsevaluatedaftersignalchangesreactivetestbenchactivity(program)postponereadonlyphase,systemverilogschedulingdetails,clock,prepone,observed,reactive,postpone,data,active,design,sample,assertions,testbench,$monitor,region,activity,100,100,101,99,time,2/24/05,driving,sampling,synchronizing,synchronizetoactiveclockedgespecifiedinclockingblockcbarb;/continueonposedgeofarbiterclksynchronizetoanyedgeofclockingblocksignalcbarb.grant;/continueonanychangeofsignal(posedgecbarb.grant);/continueonposedge(negedgecbarb.grant);/continueonnegedgewait(cbarb.grant);/waitforexpressiontruesynchronizeonmultiplesignalswith“or”(posedgecbarb.grantornegedgecbbus.error);,signalsynchronization,2/24/05,driving,sampling,synchronizing,drivesignalsfromclockingblocks:cbbus.request=1;/clockingdrivecbmandcallatm_hec.display();,2/24/05,inheritance,whydoiwantallthiscomplexity?codecantreatallcellsinthesamewaycellclassknowshowtoperformactionscell.display()printatmcelldataifimatatmcellprintethernetmcadataifimanethernetpacketprintsonetframedataifimasonetframeprintusbpacketdataifimausbpacketcodecallingdisplaydoesntneedtoknowwhattypeofcell/packetcellhandlereferencesclassesareself-contained,theyknowhowtoperformactionsonthemselvesbasedontheirtypeself-contained,robust,reusablecode.,2/24/05,classpci64extendspci32;reg63:0ad;reg7:0c_be;regpar64,req64,ack64;functionnew();endfunctionendclass/classpci64,classpci32;reg31:0ad;reg3:0c_be;regpar,frame,trdy,irdy;functionnew();endfunctionendclass/classpci32c,inheritancetoreuseexistingcode,declarebaseclassfirst,extendclasswithnewfunctionality,2/24/05,classtest5_stimextendsstim;constraintbottleneckdestinside1000:1020;endclass,classtest6_stimextendsstim;constraintthroughputdestinside0:1000,1500;endclass,inheritance:startgeneric,detailslater,declarebaseclassfirst,extendclasswithtestspecificcode,classstim;randreg31:0dest;endclass,2/24/05,inheritance:whataboutoverlap?,whatifbaseandderivedclasseshavepropertiesormethodswiththesamename?anobjecthandlefromaderivedclassaccessesthechangedpropertyormethod,overridingwhatwastherebefore,classpacket;intda,sa,datype;taskprintit();endtaskendclass,classethernetextendspacket;reg47:0da,sa;taskprintit(intdepth);endtaskendclass,2/24/05,lab2,optional:verifythememorycontroller,objectivereadchapter4ofthetutorialverifycontrollersresetverifyreadandwriteoperationsverifytheaddressmaptimeallotted1hour,2/24/05,agenda,introductiongettingstartedlanguagebasicsconnectingtoyourdutdriving,sampling,synchronizingoopbasicsrandomizationspawningprocessesfunctionalcoveragetestbenchmethodology,2/24/05,randomization,whatarewegoingtodiscuss?,whyuserandomizationrandomizationoptionsrandomizationofobjectsclassconstraintsanddistributionsin-lineconstraintsanddistributions,2/24/05,randomization,whyuserandomization?,automaticstimulusgenerationchangethecharacteristicsofthedatadrivingthedutrandomselectionoftestsrunknownvalidtestinrandomorderrandomsettingofparametersselectports,addresses,operationalparametersrandomly.directedtestingdetectsthebugsyouexpect.randomtestingdetectsthebugsyoudidnotexpect.,2/24/05,randomization,randomizationofobjects,randomvariablesrandreturnsvalueovertheentirerangerandcrandomcyclicvalueupto8bitsobjectvariablesarerandomizedbycallingtheobjectmethodrandomize().returnsa1uponsuccess.themethodisautomaticallyavailabletoclasseswithrandomvariables.youcancreatepre_randomize()andpost_randomize()methodswhichwillbeautomaticallycalledpre_randomize()setuprandomweightspost_randomize()cleanupcalculationslikecrc,2/24/05,randomization,randomizationofobjects,classpacket;randreg16:0length;randcreg7:0types;/cyclethroughalltypesrandreg7:0payload5;endclass,programtest;packetp1=new();initialbeginif(!p1.randomize()$display(“unabletorandomizep1n”);endendprogram,rand:rollingdicerandc:dealingcards,2/24/05,randomization,constrainingrandomness,purelyrandomstimulustakestoolongtodosomethinginterestingconstraintblocksallowtheinterestingsubsetofallpossiblestimulusyoucandefineseparate,non-overlappingconstraintsfordifferenttestseachpossiblesolutiontoyourconstraints,bydefault,willhaveequallikelihood,butyoucancreate“distributions”tomodifythis.constraintsanddistributionweightscanformthebasisfora“testwriterinterface”toyourtestbench,user-createdtest:-subsetoflegalstimulusvectors-subsetoflegalstimulussequences,yourtestbench:-alllegalstimulusvectors-alllegalstimulussequences,sim,2/24/05,randomization,classconstraintsanddistributions,constraintc_0length0;typeinside2:10,100:107;addrdist0:=40,1:2:=60;datadist0:/40,1:3:/60;,weightedprobabilities:=assignsweighttoeachelement:/dividesweightevenlyinrange,theconstraintblockdistributionscanbevariables,donthavetobeapercentagemultipleconstraintscanbedynamicallyenabled/disabledwithhandle.constraint_mode()errormessagesaregeneratedforunsolvableconstraints,distributionsdonothavetoaddupto100%,valuedist040/100120/100220/100320/100,valuedist040/160160/160260/160,2/24/05,randomization,in-lineconstraintsanddistributions,classtransaction;randbit31:0addr,data;constraintc1addrinside0:100,1000:2000;endclasstransactiont=new();s=t.randomize()withaddr50;addr10;/addrisforcedtobeaspecificvaluedrivebus(t);,constraintsmaybedefinedatthetimeofrandomizationresult=instance.randomize()withconstraints;allowstest-specificconstraintsin-lineconstraintsareadditivewithexistingclassconstraintssupportsallsv3.1aconstraintanddistributiondefinitions,2/24/05,randomization,thesolvercanhandlealgebraicfactoring,complexbooleanexpressions,mixedintegerandbitexpressionsandmoreallconstraintsinteractbi-directionallykeepinmindrulesregardingprecedence,signextension,truncationandwrap-aroundwhencreatingconstraints,snpshasthebestinclassconstraintsolver!,classparams;randbit20:0a,b,c,d,e,f;constraintc_0(a+b)0)endclass,2/24/05,randomization,variableordering:solvexbeforey;otherwisetbsolvesallconstraintssimultaneouslyimplicationoperator:-ex:(mode=small)-(length10);conditionaloperator:ifelseifelsebehaveslikeanormal“if”,excepttheconditionalsareevaluatedbi-directionallyglobalconstraints:xother_object.y;referencestorandobjectdatamembersintheconstraintsgetsolvedsimultaneously,constraintconstructsinsystemverilog,2/24/05,randomization,makeinstancesrandortheywontberandomizedwatchoutforsignedvariableswhatarelegalvaluesforfirstandsecond?dontrandomizeinnew()constructoralwayscheckresultofrandomize()oruse:void