电子科学与技术外文翻译.doc

电子科学与技术外文翻译 班 级： 学 号： 姓 名： 指导教师： 时 间： 34 / 34 Design of integrated 1.6 GHz, 2 W tuned RF power amplifier Abstract： This paper describes the design of an integrated tuned power amplifier specified to operate at Inmarsat satellite uplink frequencies from 1626.5 to 1660.5 MHz.The basic topology of the amplifier lies on the parallel tuned inverse class E amplifier that is modified by placing the DC-blocking capacitor into a new position and by adjusting the size of the capacitor to improve stability below the desired band. Further, the new positioning reduces losses between drain and load. The high currents flowing in the circuit made it necessary to use wide inductor width and high-Q finger capacitors in the on-chip resonator. The amplifier was implemented as a Gallium Arsenide (GaAs) integrated circuit (IC) that delivered 2 W of output power while the drain efficiency was ca. 56%.Measurements included source and load pulls to further improve the performance of the amplifier and to investigate the stability at small input drive levels.Keywords: Inverse class EPower amplifier.Self-oscillation Bias network 1 IntroductionThe usability of traditional linear amplifiers in todays high power communications systems is limited due to their low efficiency. This fact has driven the interest of research towards more efficient amplifiers such as class E 13 and inverse class E 4. Also, the demand of higher output power means higher peak currents and voltages in the drain or collector circuits. This creates high requirements for both maximum breakdown values of the transistor and to the passive circuitry of the monolithic microwave integrated circuit (MMIC). The effect of limited conductivity and limited capability to cope with heat can be minimized through careful design of MMIC. Further, emerging transistor technologies seem to withstand larger current densities and peak voltages 5, and therefore, the choice of technology is increasingly important when designing high power devices. The aim of this paper is to show experiences related to the design of switching high power radio frequency(RF) amplifiers (PA) with integrated output pulse shaping. In the second chapter the introduction to class E and inverse class E operation is revisited and the differences between the two topologies are reviewed.The third chapter describes the design of the input and output circuitry, stabilizing circuits and provides some tips to minimize timing differences at the input of a multi-finger transistor. The fourth chapter shows the final schematic and a photo of the implemented chip. The measured performance is reported in chapter five by using both basic single tone measurement equipment and a modern load pull system using multi-purpose tuners(MPT). The last section provides a summary of the article and discussion of the issues related to stabilizing circuits. 2 Class E and inverse class E amplifiers Class E and inverse class E are regarded as switching amplifiers. Ideally, in both of them the transistor is driven either on or off and this switching operation produces a series of voltage and current pulses to the output. These pulses are phase shifted and therefore do not overlap with each other. Ideal non-overlap causes the transistor to operate with drain efficiency of 100%. Classical class E drain waveforms, normalized to DC values of supply current and voltage, are shown in Fig.1.The solid line is normalized drain current waveform and the dashed line is normalized drain voltage. The requirement for optimal operation in class E is zero voltage switching (ZVS), where the drain voltage and its derivative goes to zero just before the transistor starts to conduct. In inverse class E the waveforms have swapped places so that the solid line waveform in Fig.1 is the drain voltage and the dashed line is the drain current. The optimal operation is also changed to zero-current switching (ZCS), where the current and its derivative goes smoothly to zero before the transistor enters nonconducting phase. Advantages of inverse class E over classical realization are that the drain peak voltages are lower than in classical class E and the inductance values in the output circuitry are smaller, which can save area in a MMIC chip implementation and can usually give smaller electrical series resistance (ESR) 4. Also, the possibility to accommondate series inductance as a part of resonating circuitry is useful, since the parasitic reactances can cause undamped resonances to drain waveforms 6, 7. These advantages were the reasons for choosing inverse class E topology as a starting point for our investigation. However, the tuned implementation is not traditional inverse class E, although it has similar pulsed operation. 3 Design of tuned power amplifier3.1 GaAs IC processThe IC process used is a Triquint Semiconductors pseudomorphic high electron mobility transistor (pHEMT) process named TQPED. The process utilizes both enhancement and depletion mode field effect transistors (FETs) with 0.5lm length optical lithography gates, but in our case we used only depletion mode transistors. The available depletion mode transistors have a transition frequency (Ft) of 27 GHz, drain-gate breakdown voltage of15 V and nominal pinch-off point of-0.8 V. Transistors models used are TOM3 FET models. There are several other features in the process: nichrome (NiCr) resistors for precision and bulk for high value resistors, high value MetalInsulatorMetal (MIM) capacitors, 1 local and 2thick global metal layers 8.3.2 Design of the resonator The difference between the original inverse class E in Fig.2and the final tuned topology used in our design,shown in Fig.3, is the location of blocking capacitor Cs. The original placing in Fig.2provides the DC-blocking to two directions: to the output (load) and, more important, it blocks the direct DC-current path through Lp to ground.In our case the blocking capacitor is underneath the resonating circuit as shown in Fig.3, where the Cs obstructs the flow of DC-current through Lp to ground, but not to the output (load). There is a direct way for fundamental current to flow to the output, without passing any blocking capacitor. The DC blocking capacitor can now be made significantly smaller. In our case the reduction was from100 pF to less than 50 pF, which means savings in chip area and as a secondary effect, the ability to tune a stabilizing trap to wanted frequency (more in chapter 3.2) while maintaining good amplifier performance. The design of the DC-block is now also slightly easier, since peak current flowing into the blocking branch is smaller. Furthermore,the ESR between drain and load is smaller. The fundamental current amplitudes in components Cs andLwere1.2 and 2 A, respectively. The total peak currents in the parallel resonator structure can be seen in Fig.3. The traditional inverse class E dimensioning 4 for1.6 GHz and Pout=3 W results in large chip area, as due to high Q =10 the capacitor Ctot is large (63.5 pF) anddue to high peak currents (ca. 6 A)the inductor gets physically huge. To get reasonable on-chip component values the design was gradually deviated from the design procedure in 4 by shifting it towards lower load resistance and Q value, and increasing the resonance frequency. This ended up in a dimensioning that provides clean, nonoverlapping current and voltage pulses, reasonable size passives, but which is eventually closer to class CE fundamental load 9 than to original inverse class E. The final component values of the simulation with discrete component models and an off-chip low-pass impedance matching network to 50 resulted in the following dimensioning:resistive load 4,Ctot =30 pF,Lp=0:22 nH,and L so small it could be omitted from the final design.Cs could be reduced down to 50 pF without affecting the overall performance, and it can be used to tune a stabilizing below the-carrier notch, as shown later in Fig. 8. The overall simulation results with a large switching transistor (12parallel transistors with 1850m/0.5m fingers) estimated 5.6 W output power with 72% drain efficiency. The challenge was now to maintain as good output power and efficiency while replacing the ideal circuit components with process design kit (PDK) components and while adding some stabilizing circuits to the topology.Next design problem came with the physical design of the inductor. Despite the lowered Q value the current amplitude was still so high (4.2 A peak) that ca. 200lmwide metal line was needed for the inductor, and to keep the center of the 3/4-turn inductor open it could not be made physically smaller than 0.4 nH. Hence, the capacitance Ctot and Q value were further reduced a bit, and to reduce resistive losses the capacitance Ctot was split into 12parallel high-Q capacitors. The drawn layout of the resonator structure was imported into 2.5D field simulator, and S-parameters were simulated and compared with those of the discrete simulation prototype. The unloaded phase and magnitude of the impedance data for comparisons from S-parameter simulations are shown in Figs.4and5. The phase and magnitude data of a distributed resonator is marked with a dashed line in both figures. The phases and magnitudes of the resonators follow almost the same line.When the complete amplifier was simulated, the drain efficiency was about 70% and output power was about3.4 W. The reduction in output power may be explained by parasitic resistances and by the addition of stabilizing circuits. The drain efficiency is surprisingly good despite the somewhat lowered Q and empirical output circuit design.The simulated and implemented distributed resonator is shown in Fig.6.3.3 Stabilizing the amplifier The amplifier showed a tendency of instability during large-signal S-parameter (LSSP) simulations. In the end,stability had to be evaluated through LSSP-based stability circles since unconditional stability (K1) could not be achieved without heavy losses. Stability circles were drawn throughout a frequency range of 0.55 GHz. After several simulations, a variety of stabilizing circuits had to be used to compensate ringing behaviour.First the discrete capacitor Cs was tuned to 50 pF to generate a trap in the output resonator at about 1.2 GHz frequency. This helped in achieving stability at frequencies below the frequency bandas shown by Rolletts K-factor in Fig.7. The 50 pF value was chosen for both small degradation in output power and for good stability performance. The effect of tuning of the capacitor Cs is shown in Fig. 8, where the capacitor is tuned from 30 to 70 pF. Further, 5of series resistance was added to three gate lines as shown in Fig. 9(b) to keep the amplifier stable with output standing wave ratio (SWR) range of 4.6:1. Also, a wideband RC-sink circuit was included in the input of the amplifier to reduce the gain in higher frequencies.The stable output SWR range increased with the RC filter to 22.6:1. According to the simulations the series resistances caused about 0.46 dB gain loss and the RC filter again an additional 0.67 dB. If the amplifier had to be unconditionally stable (K1), in the frequency range of 0.1 GHz to 8.0 GHz, the increase of series resistances to 9 would cause an additional 0.40 dB gain loss and more attenuation to the drive signal. The total decrease of gain due to stabilization would then be 1.53 dB, from maximum gain of 11.369.83 dB. In the implemented form, the maximum simulated gain is 10.23 dB.3.4 Input signal timing in a physically large transistor During simulations there was a noticeable phase shift between extreme fingers of the wide transistor consisting of12918 transistors with a width of 50lm each. This phase shift caused partial overlap between output pulses and decreased the drain efficiency. At that time the input network was made of a ladder-like structure shown as an example in Fig.9(a). The distance of the line between FETA and FET B is close to 1 mm, which as a pure line delay would result in about 20 ps of delay. But the delay difference was more than 80 ps and also the pulse width of the input signal was larger than predicted. Since the transistors do not switch simultaneously, they start to load each other and consume more power. The reason for increased delay and widened pulse width is the signal dependent gate capacitance that causes considerable amount of second harmonic distortion in the unterminated ladder-like input network in Fig.9(a). where the signal paths are almost equal in length.This improved the timing behaviour and the input waveform phasing in the simulations was nearly the same. Only the pulse width was still somewhat large. The equal input routing increased the drain efficiency of the amplifier from55 to 68%. The effects of gate capacitance together with additional solutions to timing problems have been published in 10. 4 Final circuitThe amplifier die sized 1.96mm 3.62 mm (WL) was glued directly to a 6mmthick aluminium heat sink. The gold-plated printed circuit board (PCB) containing output matching network and some of the gate biasing network was mounted onto the heat sink. Next the chip was wire bonded and SMA connectors were added to the circuit. The final circuit schematic is shown in Fig.10, where the dashed line is used to separate the on- and off-chip components. Lower left side in the figure is an LC-matching network which is followed by an RC-sink circuit. The RC-circuit increases the stability of the amplifier by providing a wideband loading at higher frequencies. In the gate bias circuit, upwards from the matching circuit is the parallel RLC-circuit that is a high impedance at the operating frequency while the off-chip parallel RC-circuit provides additional bias resistance in the low frequencies, thus increasing the stability of the amplifier. On the right side of the transistor, the tuned output resonator together with the off-chip matching circuit is shown. Drain supply voltage is directed through a long transmission line that is a high impedance at the operation frequency. The parallel gate RC bias circuit and output matching circuit were implemented on the PCB, which simplified the implemented chip shown in Fig. 11. Upper left box (a) is the LC input matching, lower left box (b) is the RLC bias network and on the right of the bias is the box (c)containing the RC-sink circuit. The equal length input lines are shown in the box (d), where the added series resistors(5each) show as wide sections in between the equal length lines. The transistor set is shown in box (e) and it consists of 12 transistors each of which contain 18 fingers with a width of 50lm each. The saturation current of the transistor is about 4 A. On the right from the transistor set there is the output path together with the parallel resonator in the box (f). Bonding pads are below (Gate bias), on the left (RF in) and up (RF out and drain bias). Two or three bondwires are used to minimize series resistance and inductance and also to maximize current capability of the wires. 4.1 The implemented amplifierThe implemented amplifier is shown in Fig.12togetherwith a picture of the chip layout. The resonator structure on the right side of the layout is clearly visible in the actual chip. The PCB had to be drilled open and the aluminium base plate machined for levelling the chip along the PCB surface. This way the bondwires are kept as short as possible. The PCB contains the impedance transforming network required by the output of the amplifier. Further, the supply is provided through long line that has relatively high impedance at the fundamental and has low resistance atDC. A part of the gate biasing network is also located in the PCB. The total size of the PCB is 17.1 mm37.6 mm(Width9Length). 5 Measured performance5.1 Measurement setups A single tone measurement was used to measure the amplifier output power and efficiency. An IFR 2025 signal generator and a buffer amplifier from Mini-Circuits provided the drive signal level of 25 dBm. The output was measured with a Rohde & Schwarz ZVA 8 vector spectrum analyser (VSA). The load pull measurements were performed with Focus Microwaves MPT 1820 tuners that were applied both to the input and output of the amplifier. As a source was Rohde &Schwarz SMU 200A with a buffer amplifier. The input power levels were from 15 to 25 dBm. The RF input and output powers were measured with Anritsu ML2438Apower meter with dual input. The harmonic content of the spectrum and oscillation spikes were measured with Rohde& Schwarz FSQ 40 VSA.5.2 Tuning of the amplifier In the first measurements the amplifier did not meet the simulated response. Measurements gave only 0.96 W of output power at 1575 MHz when the simulated figures were 3.4 W of output power and drain efficiency of 70%,all at supply voltage of 5.5 V. Our suspicion directed towards a scribe line that passed very close to the output resonator structure and possibly could couple the output to the input of the amplifier. The scribe line was cut with an UV-laser but this had no effect to the frequency response.The measured DC current of the amplifier was considerably higher than simulated, suggesting that the load impedance of the switching stage was too low. The impedance seen at the drain was increased by replacing a pair of 2.7 pF high-Q ceramic capacitors (Amplifier A, inTable1) in the external output matching network with on