半导体制造流程与IC产业链简介.ppt

IntroductiononFabflowandsemiconductorindustry forITrelatedemployee MorrisL YehUMC Fab8AB PEI Logic2 Outline 1 FabflowandTransistorworking 2 ICmanufacturingchain 3 Filedapplication 4 TheTrend TheRoadmap 1 1TransistorWorking 1 What stheTransistor 2 What stheTransistorstructure 3 How sthetransistorworking 4 TransistorandSystemrevolution 3 1How stheclockrunninginthetransistorring 3 2How stheinformationbroadcastinginasystem 1 What stheTransistor TransistorWorking InDigitalapplication thetransistorplaytheroleofswitchinthesystemjustlikeamechanicalswitch itmeansthatthekeycomponenttostoragethe0and1 State1 State0 ButwedeployedtheSolid StateandQuantumphysicstorealizethesolid stateswitch Transistorinsiliconindustry it smoresizeshrinkage highspeed highperformanceandlowerenergyrequiredthanthepriorarts State1 State0 2 What stheTransistorstructure TransistorWorking LDD POLY Thetransistorincluded3terminalwhichlikestheswitch 1 PolyGateplaytheroleofcontrolorinputterminal theDrainplaytheroleofoutputterminalandtheSourceplaytheroleofreferenceorground 3 How sthetransistorworking TransistorWorking VoltageontheDrainterminal output IntheDigitalapplication thetransistorbehaviorsmorelikesaCapacitor 1 DrainBias CapacitorCharge ThechargestorageontheDrainside 2 GateBias CapacitorDischarge ThestoragechargeflowfromDraintoSource3 DrainBiasagain Gatefloating CapacitorRecharge Thechargestorageagain 3 1How stheclockrunninginthetransistorring Thevideoshownthe49stagesNOTgateserieswhichconstructedtheringoscillator IntheleftNOTgatediagram iftheinputterminalbecomestate0 thePMOSwasturnON andNMOSturnedoff itmeansthattheVccflowintoOutputterminal theOutputstatebecome1 andaccordingquantumphysics thecurrentflowthechannelmeansthatelectron holepairrecombination andthelightemissionwillbedetectedbythecooledinfraredcamera TheRingOscillatorwasthetooltomeasurethesystemclockandspeed 3 2How stheinformationbroadcastinginasystem Generally there safewpeoplecouldunderstoodtheinformationbroadcastinginachip especiallyonthesystemdebug theproductengineerhardtodetectthedefectinsystemlevel Theliquid nitrogen cooledinfraredCameracoulddetectthehotspotemissionwhichgeneratedbytheelectron holepaircombination Thedefectcouldbedetectedoncethesignalflowtothedefectnode thesystemwillbeholdandhotspotfrozenonthedefectnode FIG 1 Thefirsttransistor BrattainandBardeen spnppoint contactgermaniumtransistoroperatedasaspeechamplifierwithapowergainof18onDecember23 1947 BellLabs Lucent FIG 3 TheworldwidesmallesttransistorGatelength0 061um BellLabs Lucent FIG 2 TheUMCpostgeneration0 25umstandardtransistor UMC 4 1TheTransistorrevolution TheFirstTransistor1947Belllabs TheUMC0 25umTransistor1999 UMC Theworldwideleadship2001Belllabs Lucent DeviceIntegrationandTechnologydrive 1 2Fabflow 1 Lithographyconceptandcycle 4 TransistorLayer Front end definition 5 RoutingLayer Back end definition 3 Modulecompositionandintegration 2 Moduledefinition Lithographyconcept physicalcycle ThinFilm PHOTO ETCHPhysicallayerformationcycle FabFlow Lithographyconcept Implantcycle Diffusion PHOTO DiffusionImplantlayercycle FabFlow 1 2Fabflow 1 Lithographyconceptandcycle 4 TransistorLayer Front end definition 5 RoutingLayer Back end definition 3 Modulecompositionandintegration 2 Moduledefinition Photo Rawmaterial Reticle PhotoResistEquipment I Line MUV DUV EUV Stepper SCANNER Vendors Nikon ASML 2 Moduledefinition PHOTO ThePHOTOconceptwasgeneralOpticslithographytoreproducethespecificpatterns TodaywedeployedtheUVExcimerlaserforthelight AccordingtoOpticsprinciple generallythewavelengthofthelightshouldbelessthanonetenthofhalfpitch soifthetechnologyshrink theExposurelightsourceshouldbepushedintodeeplyUVzone Thin Film Rawmaterial MetalTarget ChemicalEquipment Sputter RTP CVD AP PE LP SP MO ScubberVendors AMAT Novellus TEL ASM 2 Moduledefinition ThinFilm IngeneralwecansplittheThin Filmintotwofield oneisPhysicsdominated PVD theotherisChemicaldominated CVD ThePVDmeansthatnochemicalreactionassistedintheprocess justsimplyacceleratedAratomtobombardthetargettoevaporatethetargetanddepositonthewafer suchlikesSputter TheCVDmeansthatthechemicalreactiononthewaferorchambertodepositafilmonthesurface CVD PVD Chemicalreaction EtchRawmaterial Solvent ReactivegasEquipment DryEtch RIE WetBench ChemicalStation Vendors AMAT Novellus TEL ASM 2 Moduledefinition ETCH IngeneralwecancallthatRIEinthetermofDryetching thedryetchingwhichdominatedbythePhysicalIonbombardandchemicalreactionwiththesurfacetoevaporatedthebyproducts Reactiveionbombard DiffusionRawmaterial ChemicalGas IsotopegasEquipment Implanter FurnaceVendors Eaton Varian KE TEL 2 Moduledefinition Diffusion Inthediffusion there retwomethodstodeliverthedopantintothesiliconwafer Implant Toacceleratetheisotopeanddirectbombardthewafertodeliverthedopantintorightdepthwithrightconcentration Furnace Tousethermaldiffusionpotentialtodeliverthedopantintorightdepthwithrightconcentration CMPRawmaterial Slurry polishpadEquipment CMP W CMP Oxide CMP Cu CMP Vendors AMAT COBAT Strasbaugh 2 Moduledefinition CMP Ingeneral theCMPlikethepolisharts butdeployedthechemical mechanicalassistant There retwofactorsdominatedtheCMPprocess Firstischemicalhydrolysisslurrytohydrolyzethesurface Secondistheslurryabrasivetoremovethehydrolytewhichunderthemechanicaldominated 1 2Fabflow 1 Lithographyconceptandcycle 4 TransistorLayer Front end definition 5 RoutingLayer Back end definition 3 Moduleintegration 2 Moduledefinition ProcessFlow Layer Route Module Step 3 Moduleintegration 1 2Fabflow 1 Lithographyconceptandcycle 4 TransistorLayer Front end definition 5 RoutingLayer Back end definition 3 Modulecompositionandintegration 2 Moduledefinition BriefProcessFlow FirstLayer Diffusion P sub Siliconwafer SiN Nitrid Padoxide 1 1 WaferStart1 2 PADOxidation110A stressbuffer 1 7 SiN Nitrid Deposition1 5KA1 8 DiffusionLithography 1 8 1P R coating1 8 2StepperExposure1 8 3Development PhotoResistorcoating StepperExposure BriefProcessFlow FirstLayer Diffusion cont 1 7 Trench STI PlasmaEtching1 7 1SiNEtching1 7 2SiliconEtching1 8 PhotoResistorremove BriefProcessFlow FirstLayer Diffusion cont 1 7 APCVDSTIrefill1 7 1LinerOxideGrowth1 7 2APCVDOxidedeposition1 7 3STIFurnace1000CDensify1 8 STICMP1 9 SiNremove BriefProcessFlow Wellformation P R Coating StepperExposure 2 1N WELLFormation 2 1 1N WELLPRcoating2 1 2N WELLLithography2 1 3Development2 1 4N WELLimplant2 1 5PRstripping2 2P WELLFormation 2 2 1P WELLPRcoating2 2 2P WELLLithography2 2 3Development2 2 4P WELLimplant2 2 5PRstripping P R Coating StepperExposure N WELLImplant1 N WELL 12 N WELL 27 PMOS VT8 PMOSanti punch P WELLImplant1 P WELL 12 P WELL 27 NMOS VT8 NMOSanti punch BriefProcessFlow GateOxideandPOLY PRcoating GateOxide StepperExposure GateOxide2 UPOLYgrowth 3GateOxideFormation 3 1ThickGateOxideGrowth3 2PRcoating3 3TGLithography3 4Development3 5RCA AWetetching3 6PRstripping3 7ThinGateOxideGrowth4 PolyGrowth4 1undope POLYgrowth4 2N POLYPRcoating4 3N POLYLithography4 4Development4 5N POLYimplantandPRStrip PRCoating N POLYimplant StepperExposure BriefProcessFlow GateEngineering PRcoating StepperExposure N LDDImplant P LDDimplant 5PolyGateFormation 5 1Polyannealing5 2PRcoating5 3POLYLithography5 4Development5 5POLYGateetching5 6PRstripping5 7ThinOxideGrowth6 LDD LightDopeDrain implant6 1N LDDLithography ellipsis 6 2NLDD N PKTimplant6 3P LDDLithography ellipsis 6 4PLDD P PKTimplant BriefProcessFlow DrainEngineering P Implant N implant 7PolyGateFormation 7 1Polyannealing7 2PRcoating7 3POLYLithography7 4Development7 5POLYGateetching7 6PRstripping7 7ThinOxideGrowth8 LDD LightDopeDrain implant8 1N LDDLithography ellipsis 8 2NLDD N PKTimplant8 3P LDDLithography ellipsis 8 4PLDD P PKTimplant 1 2Fabflow 1 Lithographyconceptandcycle 4 TransistorLayer Front end definition 5 RoutingLayer Back end definition 3 Modulecompositionandintegration 2 Moduledefinition BriefProcessFlow ILDPassivation 9 SalicideFormation 9 1PETEOS 500ACapOxidedep 9 2SAB Salicide Block Lithography ellipsis 9 3Ti Cosputtering9 4SalicidationRTPC49annealing9 5SalicidationRTPC54annealing9 6TiresidualSemi toolwetclean10 ILDPassivation10 1SiN300Adeposition Moistureandsodiumblock 10 2AP USGdeposition GapfillingandB Ptrap 10 3TEOS BPSG 14Kdeposition re flowandplanarization 10 4ILDCMP PRCoating BriefProcessFlow ContactPlug Metal1 DUVStepperExposure 11 ContactPlugFormation 11 1ContactLithography11 2ContactPlasmaEtching11 3PRstrip11 4Barrierlayerdeposition Ti TiNforwellcontact 11 5RTPannealing11 6GlueLayerdeposition Ti TiNforplugadhesion 11 5WCVDfilling11 6WCMP11 7MetalLinerdeposition Ti TiNforMetaladhesion 11 8MetalSputter BriefProcessFlow Backendroutine Aluminumline CapOxide PRCoating Metal2 StepperExposure StepperExposure 12 IMDdeposition12 1HDP Oxidedeposition Gapfilling 12 2PE OxideDeposition Planarizationanduniformity 12 3IMDCMP12 4CapPE Oxide13 MVIAplugformation13 1MVIALithographycycle13 2MVIAEtchingandPRstrip13 3GlueLayerdeposition Ti TiNforplugadhesion 13 4WCVDfilling13 5WCMP13 6MetalLinerdeposition Ti TiNforMetaladhesion 13 7MetalSputter BriefProcessFlow Aluminumline BriefProcessFlow Backendroutine CopperDualDamascene PRCoating StepperExposure2 StepperExposure1 StepperExposure3 14 ILD M1Damascene14 1PEOX 3 6Kdeposition14 2M1Lithography14 3M1TrenchEtching14 4M1CuElectroplate ECP 14 5CuCMP15 M2 MVIA1DualDamascene15 1PEOX 9Kdeposition15 2M2Lithography15 3M2TrenchEtching15 4MVIA1Lithography15 5MVIA1PlugEtching15 6TrenchLinerdeposition15 7M2 MVIA1CuECP15 8CuCMP BriefProcessFlow CopperDualDamascene WhyCopper Diffusionbarrier SiN IMD Via lowkOx TrenchEtchingStop SiN IMD Trench LowkOx HardMask SiN ARCLithography SiON TrenchfirstVialastEtching CuBarrier TaN CuseedCVD CuECP CuCMP BriefProcessFlow CopperDualDamascene Outline 1 FabflowandTransistorworking 2 ICmanufacturingchain 3 Filedapplication 4 TheTrend waferprocessing 2 ICmanufacturingchain Front end IDM Fabless Turnkey Fundry 2 ICmanufacturingchain Backend AssemblyandTesting IDM SystemHouse ICDesignflow SimulationandTestbilitydesignLevel DesignVerification Physicallayoutgeneration designoptimization TestpatterngenerationLevel Tapeout DRC MaskToolingandFabPilotLevel SystemDesignEntryandAnal