4023 CMOS 三3输入与非门

October 1987 Revised June 1999 CD4023BC Buffered Triple 3 Input NAND Gate 1999 Fairchild Semiconductor CorporationDS CD4023BC Buffered Triple 3 Input NAND Gate General Description These triple gates are monolithic complementary MOS CMOS integrated circuits constructed with N and P channel enhancement mode transistors They have equal source and sink current capabilities and conform to stan dard B series output drive The devices also have buffered outputs which improve transfer characteristics by providing very high gain All inputs are protected against static dis charge with diodes to VDD and VSS Features I Wide supply voltage range 3 0V to 15V I High noise immunity 0 45 VDD typ I Low power TTL compatibility fan out of 2 driving 74L or 1 driving 74LS I 5V 10V 15V parametric ratings I Symmetrical output characteristics I Maximum input leakage 1 A at 15V over full temperature range Ordering Code Devices also available in Tape and Reel Specify by appending the suffix letter X tot he ordering code Connection Diagram Top View Block Diagram 1 3 Device Shown All Inputs Protected by Standard CMOS Input Protection Circuit Order NumberPackage Number Package Description CD4023BCMM14B14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide CD4023BCSM14D14 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide CD4023BCNN14A14 Lead Plastic Dual In Line Package PDIP JEDEC MS 001 0 300 Wide 2 CD4023BC Absolute Maximum Ratings Note 1 Note 2 Recommended Operating Conditions Note 1 Absolute Maximum Ratings are those values beyond which the safety of the device cannot be guaranteed they are not meant to imply that the devices should be operated at these limits The table of Recom mended Operating Conditions and Electrical Characteristics provides conditions for actual device operation Note 2 VSS 0V unless otherwise specified DC Electrical Characteristics Note 3 Note 3 VSS 0V unless otherwise specified Note 4 IOH and IOL are tested one output at a time DC Supply Voltage VDD 0 5 VDCto 18 VDC Input Voltage VIN 0 5 VDCto VDD 0 5 VDC Storage Temp Range TS 65 C to 150 C Power Dissipation PD Dual In Line700 mW Small Outline500 mW Lead Temperature TL Soldering 10 seconds 260 C DC Supply Voltage VDD 5 VDC to 15 VDC Input Voltage VIN 0 VDC to VDD VDC Operating Temperature Range TA 40 C to 85 C SymbolParameterConditions 40 C 25 C 85 C Units MinTypMinTypMaxMinMax IDDQuiescent Device CurrentVDD 5V1 00 0041 07 5 A VDD 10V2 00 0052 015 VDD 15V4 00 0064 030 VOLLOW Level Output VoltageVDD 5V0 0500 050 05V VDD 10V0 0500 050 05 VDD 15V0 0500 050 05 VOHHIGH Level Output Voltage VDD 5V4 954 9554 95V VDD 10V9 959 95109 95 VDD 15V14 9514 951514 95 VILLOW Level Input VoltageVDD 5V VO 4 5V1 521 51 5V VDD 10V VO 9 0V IO 1 A3 043 03 0 VDD 15V VO 13 5V4 064 04 0 VIHHIGH Level Input VoltageVDD 5V VO 0 5V3 53 533 5V VDD 10V VO 1 0V IO 1 A7 07 067 0 VDD 15V VO 1 5V11 011 0911 0 IOLLOW Level Output CurrentVDD 5V VO 0 4V0 520 440 880 36mA Note 4 VDD 10V VO 0 5V1 31 12 20 90 VDD 15V VO 1 5V3 63 082 4 IOHHIGH Level Output Current VDD 5V VO 4 6V 0 52 0 44 0 88 0 36mA Note 4 VDD 10V VO 9 5V 1 3 1 1 2 2 0 90 VDD 15V VO 13 5V 3 6 3 0 8 2 4 IINInput CurrentVDD 15V VIN 0V 0 3 10 5 0 3 1 0 A VDD 15V VIN 15V0 310 50 31 0 CD4023BC AC Electrical Characteristics Note 5 TA 25 C CL 50 pF RL 200k unless otherwise specified Note 5 AC Parameters are guaranteed by DC correlated testing Note 6 CPD determines the no load AC power consumption of any CMOS device For complete explanation see Family Characteristics Application Note AN 90 SymbolParameterConditionsMinTypMaxUnits tPHLPropagation Delay HIGH to LOW LevelVDD 5V130250ns VDD 10V60100 VDD 15V4070 tPLHPropagation Delay LOW to HIGH LevelVDD 5V110250ns VDD 10V50100 VDD 15V3570 tTHL Transition TimeVDD 5V90200ns tTLHVDD 10V50100 VDD 15V4080 CINAverage Input CapacitanceAny Input57 5pF CPDPower Dissipation Capacity Note 6 Any Gate17pF 4 CD4023BC Physical Dimensions inches millimeters unless otherwise noted 14 Lead Small Outline Integrated Circuit SOIC JEDEC MS 013 0 300 Wide Package Number M14B 14 Lead Small Outline Package SOP EIAJ TYPE II 5 3mm Wide Package Number M14D Fairchild does not assume any responsibility for use of any circuitry described no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications CD4023BC Buffered Triple 3 Input NAND Gate LIFE SUPPORT POLICY FAIRCHILD S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION As used herein 1 Life support devices or systems are devices or systems which a are intended for surgical implant into the body or b support or sustain life and c whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be rea sonably expected to result in a significant injury to the user 2 A critical component in any component of a life support device or system whose failure to perform can be rea sonabl