集成逻辑门电路及组合电路.doc

Experiment 9 Combinatorial Logic CircuitsI Objectives1 To understand the configurations of integrated circuits;2 To verify the logic functions of TTL, CMOS integrated circuits;3 To understand the logic functions of full-adder and half-adder and know how to implement by logic elements;4 To hold the methods of designing and implementing combinatorial logic circuits.II Apparatus and EquipmentsNameSpec.Number1DC source12analog experiment systemMES-13Multi-meter14Integrated circuits4 two inputs “NAND” gate74LS00154 two inputs “NOR” gate74LS0216Double four-inputs “NAND” gate 74LS20174 two inputs “AND” gate 74LS08186 inverter 74LS04194 two inputs “OR” gate 74LS321104 two inputs “exclusive-OR” gate 74LS86111Double four-inputs “NOR” gate CD40021III Principle of the Experiment1 To study the configurations of the chips;2 To fill in the vacancies1) The operation voltage of the 74LS TTL integrated circuit（ ）, the logic high level of voltage 1 is （ ）volts, the logic low level of voltage 0 is （ ）volts;2) If there is no input signal, TTL gate circuit can be regarded as（ ）; and it can be regarded as （ ） when it is pulled out from or inserted into slots.3)CMOS integrated circuits: A. the voltage range of CD4000series is（ ）;B. the voltage range of CD000series is（ ）;3 To design a vote-circuit with three inputs and one output, of which the output follows the most of inputs: 1) List the logic table and give the simplest logic expressions with AND-OR gates;2)Implement the circuit with the given chips and draw the logic diagram (the chips and gates are limited to least);3）Verify the function and draw the state-table;4 To design a half-adder (the requirements should be same as that of procedure “3”); 5 To design a full-adder To design a half-adder (the requirements should be same as that of procedure “3”);6 To design a logic answer-circuit : three inputs are A, B, and C; three outputs are , , and ; and the logic relationship are =A, =B, and =CinputsoutputsABC100100010010001001IV Lab Work1 Logic functions verification of TLL gate circuits;2 Logic functions verification of CMOS gate circuits; 3 Logic functions test of logic vote-circuit;4 Logic functions verification of the half-adder & full-adder;5 Logic functions verification of logic answer-circuit. V Requirements of the Experiment Report1 Filling in the tables, verifying the logic circuit, and comparing & analyzing the results;2 Discussing the input pins of gate circuits.实验九 集成逻辑门电路及组合电路一、实验目的1了解集成电路的外引线排列及其使用方法。2验证常用TTL、CMOS集成门电路逻辑功能，掌握其逻辑符号。3掌握半加器，全加器的逻辑功能，并选用元件实现之。4掌握组合电路的设计和实现方法二、实验仪器设备名 称规格，型号数量1直流稳压源1台2数字电子技术实验系统1台3万用表1台4集成电路四2输入与非门74LS001片四2输入或非门74LS021片双四输入与非门74LS201片四2输入与门74LS081片六反相器74LS041片四二输入或门74LS321片四2输入异或门74LS861片双四输入或非门CD40021片三、预习要求1画好实验用各芯片管脚图。2完成下列填空1)74LS(74)系列TTL集成电路的工作电压为（ ），逻辑高平1时（ ），低电平0时（ ）2)TTL门电路输入端不接信号时，视为（ ），在拔插集成块时，（ ）。3)CMOS集在成电路中：A.CD4000系列电源电压范围为（ ）;B.CD000系列电源电压为（ ）3设计一个多数表决器电路，该电路有三个输入端，一个输出端，其功能是输出电平与输入信号的多数电平一致，要求如下：1)列写真值表，写出最简的与或逻辑表达式；2)用提供的芯片实现电路，要求使用的芯片最少，门数最少，画出实现的逻辑电路图；3）画出验证此功能的状态表格。4设计一个半加器，即只考虑两个加数本身相加，不考虑从低位来的进位，要求如上3。 5设计一个全加器，即不仅要考虑两个加数本身相加，还要考虑从低位来的进位，要求如上3。6抢答显示器的设计，它的控制要求为：现有三组竞赛者参加抢答竞赛，每组竞赛都有一个抢答按扭开关，竞赛者要抢答问题则需抢先拔动开关，则抢先回答者对应的显示器就发光，而后拔动开关者无效。设计提示：设输入变量A、B、C分别代表三组竞赛者，输出、分别表示A、B、C三组的抢答显示指示灯。设首先拔动开关者为1，则A、B、C只有三种状态，即为100，010，001，在抢答者拔动开关后，必须用它的输出同时去切断另两组的输出信号，其抢答状态如表，据此表写出其逻辑表达式，并画出用与非门器件实现的逻辑图。（=A；=B；=C）输 入输 出ABC100100010010001001四、实验任务与方法1TLL门电路逻辑功能验证在数字实验装置上安装好TLL门电路芯片，该芯片输入端接逻辑开关，输出端接LED发光二极管，检查无误后接通稳压电源“5V”。按状态表输入信号，现定输出结果（LED发光二极管）灯亮为1，灯灭为0，填入自拟表格中，并用万用表测0，1电平值。2CMOS门电路逻辑功能验证 CMOS门电路逻辑功能验证方法同TLL门电路，需注意其不用的输入端管脚不能悬空要接地，当输入端需改变接连线时，需切断电源。3表决电路的逻辑功能的测试对照预习中设计的表决器的电路，按所