DE2 实验练习解答—lab4 counters【verilog】【digital logic】.docx

/halflife/archive/2010/06/04/1751214.html本练习的目的是使用计数器。Part I 用T触发器实现16-bit的计数器参照图 1所示的4-bit的同步计数器，实现一个16-bit 的计数器。代码 1 /top-level file 2 module part1(KEY0,SW,HEX3,HEX2,HEX1,HEX0); 3 input KEY0; /时钟脉冲 4 input 1:0SW; /使能&复位 5 output 6:0HEX3,HEX2,HEX1,HEX0; /输出显示 6 wire 15:0q; /16-bit计数输出 7 8 counter_16(SW1,KEY0,SW0,q); 9 10 seg7_lut H0(q3:0,HEX0);11 seg7_lut H1(q7:4,HEX1);12 seg7_lut H2(q11:8,HEX2);13 seg7_lut H3(q15:12,HEX3);14 15 endmodule 1 /由T触发器构建的16-bit计数器 2 module counter_16(en,clk,clr,Q); 3 input en,clk,clr; 4 wire 15:0q; 5 output 15:0Q; 6 t_ff u0(en,clk,clr,q0); 7 t_ff u1(en&q0,clk,clr,q1); 8 t_ff u2(en&q0&q1,clk,clr,q2); 9 t_ff u3(en&q0&q1&q2,clk,clr,q3);10 t_ff u4(en&q0&q1&q2&q3,clk,clr,q4);11 t_ff u5(en&q0&q1&q2&q3&q4,clk,clr,q5);12 t_ff u6(en&q0&q1&q2&q3&q4&q5,clk,clr,q6);13 t_ff u7(en&q0&q1&q2&q3&q4&q5&q6,clk,clr,q7);14 t_ff u8(en&q0&q1&q2&q3&q4&q5&q6&q7,clk,clr,q8);15 t_ff u9(en&q0&q1&q2&q3&q4&q5&q6&q7&q8,16 clk,clr,q9);17 t_ff u10(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9,18 clk,clr,q10); 19 t_ff u11(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10,20 clk,clr,q11); 21 t_ff u12(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11,22 clk,clr,q12); 23 t_ff u13(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12,24 clk,clr,q13); 25 t_ff u14(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12&q13,26 clk,clr,q14); 27 t_ff u15(en&q0&q1&q2&q3&q4&q5&q6&q7&q8&q9&q10&q11&q12&q13&q14,28 clk,clr,q15); 29 30 assign Q=q; 31 32 endmodule 1 /T flip flop 2 module t_ff(t,clk,rst_n,q); 3 input t,clk,rst_n; 4 output reg q; 5 6 always (posedge clk) 7 begin 8 if(!rst_n) 9 q=0;10 else 11 begin12 if(t=1b1)13 q=q;14 else 15 q=q;16 end 17 end18 19 endmodule 图值图占用的数量Part用赋值语句实现-计数器代码 1 /counter-16bit 2 module part2(clk,rst_n,q); 3 input clk,rst_n; 4 output reg 15:0q; 5 6 always (posedge clk) 7 begin 8 if(!rst_n) 9 q=1b0;10 else 11 begin12 if(q=65535)13 q=0;14 else15 q=q+1;16 end17 end18 19 endmodule图-计数器的视图图值图-计数器占用的Part用实现-计数器代码1 /Top-level file2 module counter_lpm(en,clk,clr,q);3 input en,clk,clr;4 output 15:0q;5 6 megcounter counter_16bit(.clock(clk),.cnt_en(en),.sclr(clr),7 .q(q)8 );9 endmodule 1 / synopsys translate_off 2 timescale 1 ps / 1 ps 3 / synopsys translate_on 4 module megcounter ( 5 clock, 6 cnt_en, 7 sclr, 8 q); 9 10 input clock;11 input cnt_en;12 input sclr;13 output 15:0 q;14 15 wire 15:0 sub_wire0;16 wire 15:0 q = sub_wire015:0;17 18 lpm_counter lpm_counter_component (19 .sclr (sclr),20 .clock (clock),21 .cnt_en (cnt_en),22 .q (sub_wire0),23 .aclr (1b0),24 .aload (1b0),25 .aset (1b0),26 .cin (1b1),27 .clk_en (1b1),28 .cout (),29 .data (161b0),30 .eq (),31 .sload (1b0),32 .sset (1b0),33 .updown (1b1);34 defparam35 lpm_counter_component.lpm_direction = UP,36 lpm_counter_component.lpm_port_updown = PORT_UNUSED,37 lpm_counter_component.lpm_type = LPM_COUNTER,38 lpm_counter_component.lpm_width = 16;39 40 41 endmodule图用实现-计数器所占用的Part循环显示-在上循环显示-，每秒刷新一次。代码 1 /top-level file 2 module seg_number( 3 output 6:0HEX0, 4 input CLOCK_50, 5 input 0:0KEY 6 ); 7 8 wire clk_1hz; 9 reg 3:0cnt; 10 11 div u0( 12 .o_clk(clk_1hz), 13 .i_clk(CLOCK_50), 14 .rst_n(KEY) 15 ); 16 17 always (posedge clk_1hz or negedge KEY) 18 begin 19 if(!KEY) 20 cnt=4b0; 21 else 22 begin 23 if(cnt=4d9) 24 cnt=4b0; 25 else 26 cnt=cnt+1b1; 27 end 28 end 29 30 seg7_lut u1( 31 .oseg(HEX0), 32 .idig(cnt3:0) 33 ); 34 endmodule 35 36 /divider 37 module div( 38 output reg o_clk, 39 input rst_n, 40 input i_clk 41 ); 42 43 parameter N=50_000_000; 44 parameter M=24_999_999; 45 46 reg 25:0cnt; 47 48 always (posedge i_clk or negedge rst_n) 49 begin 50 if(!rst_n) 51 cnt=26b0; 52 else 53 begin 54 if(cnt=N-1) 55 cnt=26b0; 56 else 57 cnt=cnt+26b1; 58 end 59 end 60 always (posedge i_clk or negedge rst_n) 61 begin 62 if(!rst_n) 63 o_clk=0; 64 else 65 begin 66 if(cnt=M) 67 o_clk=1; 68 else 69 o_clk=0; 70 end 71 end 72 73 endmodule 74 75 /seg7_lut 76 module seg7_lut ( 77 output reg 6:0 oseg, 78 input 3:0 idig 79 ); 80 always (idig) 81 begin 82 case (idig) 83 4h1: oseg = 7b1111001; / -t- 84 4h2: oseg = 7b0100100; / | | 85 4h3: oseg = 7b0110000; / lt rt 86 4h4: oseg = 7b0011001; / | | 87 4h5: oseg = 7b0010010; / -m- 88 4h6: oseg = 7b0000010; / | | 89 4h7: oseg = 7b1111000; / lb rb 90 4h8: oseg = 7b0000000; / | | 91 4h9: oseg = 7b0011000; / -b- 92 4ha: oseg = 7b0001000; 93 4hb: oseg = 7b0000011; 94 4hc: oseg = 7b1000110; 95 4hd: oseg = 7b0100001; 96 4he: oseg = 7b0000110; 97 4hf: oseg = 7b0001110; 98 default: oseg = 7b1000000; 99 endcase100 end101 endmodule Part循环显示在上循环显示，如图所示。图个上循环显示代码top-level file 1 /top-level file 2 module hello(HEX7,HEX6,HEX5,HEX4, 3 HEX3,HEX2,HEX1,HEX0, 4 CLOCK_50,KEY); 5 input CLOCK_50; 6 input 0:0KEY; 7 output 6:0HEX7,HEX6,HEX5,HEX4,HEX3,HEX2, 8 HEX1,HEX0; 9 10 wire clk_1hz;11 reg 3:0cnt;12 13 div u0(.o_clk(clk_1hz),14 .rst_n(KEY),15 .i_clk(CLOCK_50)16 );17 18 always (posedge clk_1hz or negedge KEY)19 begin20 if(!KEY)21 cnt=4b0;22 else 23 begin24 if(cnt=4b0111)25 cnt=4b0;26 else27 cnt=cnt+1b1;28 end29 end30 31 seg7_h0 h0(.oseg(HEX0),32 .idig(cnt)33 );34 seg7_h1 h1(.oseg(HEX1),35 .idig(cnt)36 );37 seg7_h2 h2(.oseg(HEX2),38 .idig(cnt)39 );40 seg7_h3 h3(.oseg(HEX3),41 .idig(cnt)42 );43 seg7_h4 h4(.oseg(HEX4),44 .idig(cnt)45 );46 seg7_h5 h5(.oseg(HEX5),47 .idig(cnt)48 );49 seg7_h6 h6(.oseg(HEX6),50 .idig(cnt)51 );52 seg7_h7 h7(.oseg(HEX7),53 .idig(cnt)54 ); 55 endmodule分频器 1 /divider 2 module div( 3 output reg o_clk, 4 input rst_n, 5 input i_clk 6 ); 7 8 parameter N=50_000_000; 9 parameter M=24_999_999;10 11 reg 25:0cnt;12 13 always (posedge i_clk or negedge rst_n)14 begin15 if(!rst_n)16 cnt=26b0;17 else18 begin19 if(cnt=N-1)20 cnt=26b0;21 else22 cnt=cnt+26b1;23 end24 end25 always (posedge i_clk or negedge rst_n)26 begin27 if(!rst_n)28 o_clk=0;29 else30 begin31 if(cnt=M)32 o_clk=1;33 else34 o_clk=0;35 end36 end37 38 endmodule译码0 1 /seg7_lut 2 module seg7_h0 3 ( 4 output reg 6:0 oseg, 5 input 3:0 idig 6 ); 7 always (idig) 8 begin 9 case (idig)10 4h0: oseg = 7b1000000; /O11 /4h1: oseg = 7b1111001; 12 /4h2: oseg = 7b0100100; 13 /4h3: oseg = 7b0110000; 14 4h4: oseg = 7b000100