用FPGA实现SRAM读写控制的Verilog代码.doc

define SRAM_SIZE 8timescale 1ns/1ns/FOR SRAM INTERFACE CONTROLmodule SRAM_INTERFACE(in_data,/INPUT DATA out_data,/OUTPUT DATA fiford,/FIFO READ CONTROL LOW VOLTAGE fifowr,/FIFO WRITE CONTROL LOW VOLTAGE nfull, nempty, address,/SENT SRAM ADDRESS BUS sram_data,/SRAM DATA BUS rd,/SRAM READ SINGAL ENABLE LOW VOLTAGE wr,/SRAM WRITE ENABLE LOW VOLTAGE clk,/system clk rst);/global reset singal,low voltageinput fiford,fifowr,clk,rst;input7:0 in_data;output7:0 out_data;reg7:0 in_data_buf,out_data_buf;/input and output bufferoutput reg nfull,nempty;output rd,wr;inout7:0 sram_data;output reg 10:0address;reg10:0 fifo_wp,fifo_rp;reg10:0fifo_wp_next,fifo_rp_next;reg near_full,near_empty;reg3:0 state;parameter idle=4b0000, read_ready=b0100, read=b0101, read_over=b0111, write_ready=b1000, write=b1001, write_over=b1011;always(posedgeclk or negedge rst)begin if(!rst) state=idle; else case(state) idle:begin if(fifowr=0&nfull) state=write_ready; else if(fiford=0&nempty) state=read_ready; else state=idle; end read_ready: state=read; read:begin if(fiford=1) state=read_over; else state=read; end read_over: state=idle; write_ready: state=write; write:begin if(fifowr=1) state=write_over; else state=write; end write_over: state=idle; default:state=idle; endcaseendassign rd=state2;assign wr=(state=write)?fifowr:1b1;always(posedgeclk)begin if(fifowr) in_data_buf=in_data;end/=always(stateor fiford or fifowr or fifo_wp or fifo_rp)begin if(state2|fiford) address=fifo_rp; else if(state3|fifowr) address=fifo_wp; else address=bz;end/=assign out_data=(state2)?sram_data:8bz;always(posedgeclk)begin if(state=read) out_data_buf=sram_data;end/=always(posedgeclk or negedge rst)begin if(!rst) fifo_rp=0; else if(state=read_over) fifo_rp=fifo_rp_next;end/=always(fifo_rp)begin if(fifo_rp=SRAM_SIZE-1) fifo_rp_next=0; else fifo_rp_next=fifo_rp+1;end/=always(posedgeclk or negedge rst)begin if(!rst) fifo_wp=0; else if(state=write_over) fifo_wp=fifo_wp_next;end/=always(fifo_wp)begin if(fifo_wp=SRAM_SIZE-1) fifo_wp_next=0; else fifo_wp_next=fifo_wp+1;end/=always(posedgeclk or negedge rst)begin if(!rst) near_empty=1b0; else if(fifo_wp=fifo_rp_next) near_empty=1b1; else near_empty=1b0;end/=always(posedgeclk or negedge rst)begin if(!rst) nempty=1b0; else if(near_empty&state=read) nempty=1b0; else if(state=write) nempty=1b1;end/=always(posedgeclk or negedge rst)begin if(!rst) near_full=1b0; else if(fifo_rp=fifo_wp_next) near_full=1b1; else near_full=1b0;end/=always(posedgecl