华为静态时序分析与逻辑设计.pdf

BTS 2 BTS 2003 4 Version 1 0 0 12Timing Analyzer3 0 673 Static Timing Analysis STA AB AB f 1 T DQDQ CD CLK INPUT tCO tDELAY tSU OUT Setup Hold time V0Setup time3tSU R z PY V G 5 J K LMN AN42 Metastability in Altera Devices Clock Skew Clock Skew R 01 R2 A Off Chip Delay Off Chip Delay 6 PW3 Rtu PW3 R 45 F g DFF z R R V FG Timing Analyzer Timing Analyzer Registered Performance AB AB P A F R R BCD E6 5F V FG Timing Analyzer Timing Analyzer Registered Performance 10 5 ns tuij V q T tCO tDELAY tSU vMAX7000A E datasheet EPM7256AEQC208 10 K tCOwxyz tRD B1 6ns0 tSUwxyz tSU B2 9ns0 w 4 Q 5 D 5 cdBN cd tDELAY 4 Q 5 D 5 V vDelay Matrixab tDELAYB6 0ns T tCO tDELAY tSU 1 6ns 6 0ns 2 9ns 10 5ns H PrimeTime 0123 45 FG PrimeTime PrimeTime Synopsys 89 G H IJKL PrimeTime zMASIC sign off N89 hiEDA89 IC O FPGA S PrimeTime 5 Arrival Time PQBC Eh 4 f RM V N f 45 VSD T 45D UV VF H Required Arrival Time RAT PQ 4 f WP n V Slack PQ 4 f WP n V BC V V X Slack YPQT Z Z IJKL MN1 1 QA QB QC QD RCO A LDN B C D ENT ENP CLK CLRN 74162 COUNTER MAX plus II Timing Analyzer 74162 8 0 74162 5 4 jk 3 EPF6024AQC240 3 MN2 MAX plus II Timing Analyzer TMU 5 R 8 EPF6024AQC240 3 FG PrimeTime PrimeTime Xilinx FG PrimeTime PrimeTime Altera B F 6 K Altera Xilinx FPrimeTime set search path QUARTUS ROOTDIR eda synopsys primetime lib set link path alt vtl db apex20ke asynch mem lib db apex20ke lvds receiver lib db apex20ke cam lib db apex20ke lvds transmitter lib db apex20ke io lib db apex20ke pll lib db apex20ke lcell lib db apex20ke pterm lib db read verilog QUARTUS ROOTDIR eda synopsys primetime lib apex20ke camslice pt v read verilog QUARTUS ROOTDIR eda synopsys primetime lib apex20ke ramslice pt v read verilog snug pt vo current design snug link design snug read sdf snug v sdo FG PrimeTime PrimeTime Altera Script create clock CLK period 4 waveform 0 2 check timing report analysis coverage report timing FG PrimeTime PrimeTime Altera Script FG PrimeTime PrimeTime Xilinx FPGA 01 TIGset false path 45 MAXDELAYset max delay F OFFSET OUTset output delay F OFFSET INset input delay F PERIODcreate clock R UCF SDC SDC Synopsys Design Constraints UCF Xilinx User Constraints File FG PrimeTime 23 45 clock delay 1 max data path clock delay 2 tsu 6 clock period FG PrimeTime 23 45 Global Clock k Clock delay 6 B 0ns Max data path tCO 5 5 cd V tsu 34 5 Clock Delay 1 0ns Clock Delay 2 0ns Max Data Path tco of source reg path between reg 1 449ns 258ns 1 707ns With 4ns clock period the slack is 4ns 1 707ns 2 293ns FG PrimeTime 23 45 FG PrimeTime 23 45 PrimeTimeab METs1234 5 VIOLATEDs 12 78 45 FG PrimeTime clock delay 1 minimum data delay clock delay 2 th 9 0 78 45 FG PrimeTime Global Clock k Clock delay 6 B 0ns Min data path tCO 5 5 cd V th 34 5 Clock Delay 1 0ns Clock Delay 2 0ns Minimum Data Path tco of source reg path between reg 1 449ns